ADSP-BF608BBCZ-5 Datasheet, PDF (59/112 Pages) Analog Devices – Blackfin Dual Core Embedded Processor

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 26 and Figure 10 describe clock and reset operations. Per
the CCLK, SYSCLK, SCLK0, SCLK1, DCLK, and OCLK timing
specifications in Table 17 on Page 53, combinations of 
SYS_CLKIN and clock multipliers must not select clock rates in
excess of the processor’s maximum instruction rate.
Table 26. Clock and Reset Timing
Parameter
Min
Timing Requirements
f_CKIN
f_CKIN
t_CKINL
t_CKINH
t_WRST
SYS_CLKIN Frequency (using a crystal)^{1, 2, 3}
SYS_CLKIN Frequency (using a crystal oscillator)^{1, 2, 3}
SYS_CLKIN Low Pulse¹
SYS_CLKIN High Pulse¹
SYS_HWRST Asserted Pulse Width Low⁴
20
20
6.67
6.67
11 × t_CKIN
1 _{Applies to PLL bypass mode and PLL non bypass mode.}
2 _{The tCKIN period (see Figure 10) equals 1/fCKIN.}
3 _{If the CGU_CTL.DF bit is set, the minimum fCKIN specification is 40 MHz.}
4 _{Applies after power-up sequence is complete. See Table 27 and Figure 11 for power-up reset timing.}
V_{DD_EXT}
1.8 V/3.3 V Nominal
Max
50
60
Unit
MHz
MHz
ns
ns
ns
SYS_CLKIN
t_CKIN
t_CKINL
t_CKINH
SYS_HWRST
t_WRST
Figure 10. Clock and Reset Timing
Rev. 0 | Page 59 of 112 | June 2013