ADSP-BF608BBCZ-5 Datasheet, PDF (26/112 Pages) Analog Devices – Blackfin Dual Core Embedded Processor

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
Description
Port
LP3_D6
LP3 Data 6
F
LP3_D7
LP3 Data 7
F
PA_00 – PA_15
PORTA Position 00 through PORTA Position 15
A
PB_00 – PB_15
PORTB Position 00 through PORTB Position 15
B
PC_00 – PC_15
PORTC Position 00 through PORTC Position 15
C
PD_00 – PD_15
PORTD Position 00 through PORTD Position 15
D
PE_00 – PE_15
PORTE Position 00 through PORTE Position 15
E
PF_00 – PF_15
PORTF Position 00 through PORTF Position 15
F
PG_00 – PG_15
PORTG Position 00 through PORTG Position 15
G
PPI0_CLK
EPPI0 Clock
E
PPI0_D00
EPPI0 Data 0
F
PPI0_D01
EPPI0 Data 1
F
PPI0_D02
EPPI0 Data 2
F
PPI0_D03
EPPI0 Data 3
F
PPI0_D04
EPPI0 Data 4
F
PPI0_D05
EPPI0 Data 5
F
PPI0_D06
EPPI0 Data 6
F
PPI0_D07
EPPI0 Data 7
F
PPI0_D08
EPPI0 Data 8
F
PPI0_D09
EPPI0 Data 9
F
PPI0_D10
EPPI0 Data 10
F
PPI0_D11
EPPI0 Data 11
F
PPI0_D12
EPPI0 Data 12
F
PPI0_D13
EPPI0 Data 13
F
PPI0_D14
EPPI0 Data 14
F
PPI0_D15
EPPI0 Data 15
F
PPI0_D16
EPPI0 Data 16
E
PPI0_D17
EPPI0 Data 17
E
PPI0_D18
EPPI0 Data 18
E
PPI0_D19
EPPI0 Data 19
E
PPI0_D20
EPPI0 Data 20
D
PPI0_D21
EPPI0 Data 21
D
PPI0_D22
EPPI0 Data 22
E
PPI0_D23
EPPI0 Data 23
E
PPI0_FS1
EPPI0 Frame Sync 1 (HSYNC)
E
PPI0_FS2
EPPI0 Frame Sync 2 (VSYNC)
E
PPI0_FS3
EPPI0 Frame Sync 3 (FIELD)
E
PPI1_CLK
EPPI1 Clock
B
PPI1_D00
EPPI1 Data 0
C
PPI1_D01
EPPI1 Data 1
C
PPI1_D02
EPPI1 Data 2
C
PPI1_D03
EPPI1 Data 3
C
PPI1_D04
EPPI1 Data 4
C
PPI1_D05
EPPI1 Data 5
C
PPI1_D06
EPPI1 Data 6
C
PPI1_D07
EPPI1 Data 7
C
Rev. 0 | Page 26 of 112 | June 2013
Pin Name
PF_14
PF_15
PA_00 – PA_15
PB_00 – PB_15
PC_00 – PC_15
PD_00 – PD_15
PE_00 – PE_15
PF_00 – PF_15
PG_00 – PG_15
PE_09
PF_00
PF_01
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PF_08
PF_09
PF_10
PF_11
PF_12
PF_13
PF_14
PF_15
PE_03
PE_04
PE_00
PE_01
PD_12
PD_15
PE_02
PE_05
PE_08
PE_07
PE_06
PB_14
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07