ADSP-BF608BBCZ-5 Datasheet, PDF (69/112 Pages) Analog Devices – Blackfin Dual Core Embedded Processor

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DDR2 SDRAM Write Cycle Timing
Table 38. DDR2 SDRAM Write Cycle Timing, V_{DD_DMC} Nominal 1.8 V
Parameter
Switching Characteristics
t_DQSS2
t_DS
t_DH
t_DSS
DMC0_DQS Latching Rising Transitions to Associated Clock Edges
Last Data Valid to DMC0_DQS Delay
DMC0_DQS to First Data Invalid Delay
DMC0_DQS Falling Edge to Clock Setup Time
t_DSH
DMC0_DQS Falling Edge Hold Time From DMC0_CK
t_DQSH
DMC0_DQS Input High Pulse Width
t_DQSL
DMC0_DQS Input Low Pulse Width
t_WPRE
Write Preamble
t_WPST
Write Postamble
t_IPW
Address and Control Output Pulse Width
t_DIPW
DMC0_DQ and DMC0_DM Output Pulse Width
1 _{In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.}
2 _{Write command to first DMC0_DQS delay = WL × tCK + tDQSS.}
Min
–0.15
0.15
0.3
0.25
0.25
0.35
0.35
0.35
0.4
0.6
0.35
250 MHz¹
Max
0.15
Unit
t_CK
ns
ns
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
DMC0_CK
DMC0_A00
DMC0_LDQS
DMC0_UDQS
DMC0_LDM
DMC0_UDM
t_IPW
t_DQSS
t_DSH
t_WPRE
t_DS
t_DH
t_DSS
t_DQSL
t_DQSH
t_DIPW
t_WPST
Figure 21. DDR2 SDRAM Controller Output AC Timing
Rev. 0 | Page 69 of 112 | June 2013