ADSP-BF608BBCZ-5 Datasheet, PDF (22/112 Pages) Analog Devices – Blackfin Dual Core Embedded Processor

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 6. Detailed Signal Descriptions (Continued)
Signal Name
SPT_BD1
SPT_BFS
SPT_BTDV
SYS_BMODEn
SYS_CLKIN
SYS_CLKOUT
SYS_EXTWAKE
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_IDLEn
SYS_NMI
SYS_PWRGD
SYS_RESOUT
SYS_SLEEP
SYS_TDA
SYS_TDK
SYS_XTAL
TMR_ACIn
TMR_ACLKn
TMR_CLK
TMR_TMRn
TWI_SCL
TWI_SDA
UART_CTS
UART_RTS
UART_RX
UART_TX
USB_CLKIN
USB_DM
USB_DP
USB_ID
USB_VBC
USB_VBUS
Direction
I/O
I/O
Output
Input
Input
Output
Output
I/O
I/O
Input
Output
Input
Input
Output
Output
Input
Input
Output
Input
Input
Input
I/O
I/O
I/O
Input
Output
Input
Output
Input
I/O
I/O
Input
Output
I/O
Description
Channel B Data 1 Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
Channel B Frame Sync The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
Channel B Transmit Data Valid This signal is optional and only active when SPORT is configured in
multi-channel transmit mode. It is asserted during enabled slots.
Boot Mode Control n Selects the boot mode of the processor.
Clock/Crystal Input Connect to an external clock source or crystal.
Processor Clock Output Outputs internal clocks. Clocks may be divided down. See the CGU chapter in
the processor hardware reference for more details.
External Wake Control Drives low during hibernate and high all other times. Typically connected to the
enable input of the voltage regulator controlling the V_{DD_INT} supply.
Complementary Fault Complement of SYS_FAULT.
Fault Indicates internal faults or senses external faults depending on the operating mode.
Processor Hardware Reset Control Resets the device when asserted.
Core n Idle Indicator When low indicates that core n is in idle mode or being held in reset.
Non-maskable Interrupt Priority depends on the core that receives the interrupt. See the processor
hardware and programming references for more details.
Power Good Indicator When high it indicates to the processor that the V_{DD_INT} level is within specifica-
tions such that it is safe to begin booting upon return from hibernate.
Reset Output Indicates that the device is in the reset state.
Processor Sleep Indicator When low indicates that the processor is in the deep sleep power saving
mode.
Thermal Diode Anode May be used by an external temperature sensor to measure the die temperature.
Thermal Diode Cathode May be used by an external temperature sensor to measure the die
temperature.
Crystal Output Drives an external crystal. Must be left unconnected if an external clock is driving CLKIN.
Alternate Capture Input n Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.
Alternate Clock n Provides an additional time base for use by an individual timer.
Clock Provides an additional global time base for use by all the GP timers.
Timer n The main input/output signal for each timer.
Serial Clock Clock output when master, clock input when slave.
Serial Data Receives or transmits data.
Clear to Send Flow control signal.
Request to Send Flow control signal.
Receive Receive input. Typically connects to a transceiver that meets the electrical requirements of the
device being communicated with.
Transmit Transmit output. Typically connects to a transceiver that meets the electrical requirements of
the device being communicated with.
Clock/Crystal Input This clock input is multiplied by a PLL to form the USB clock. See Universal Serial
Bus (USB) On-The-Go—Receive and Transmit Timing for frequency/tolerance information.
Data – Bidirectional differential data line.
Data + Bidirectional differential data line.
OTG ID Senses whether the controller is a host or device. This signal is pulled low when an A-type plug
is sensed (signifying that the USB controller is the A device), but the input is high when a B-type plug is
sensed (signifying that the USB controller is the B device).
VBUS Control Controls an external voltage source to supply VBUS when in host mode. May be
configured as open drain. Polarity is configurable as well.
Bus Voltage Connects to bus voltage in host and device modes.
Rev. 0 | Page 22 of 112 | June 2013