CN0269 Datasheet, PDF (8/12 Pages) Analog Devices – Devices Connected

CN-0269
Circuit Note
AI
R_P
R_S
i_{P +}
e_Rp
e_Rs
e_{V AD8065}
i_{N –}
R_f
e_Rf
Figure 13. AD8065 Noise Model
The noise sources shown in Figure 13 must be converted to the
output by multiplying the noise gain, which is 1 for a unity-gain
buffer.
e = AD8065_RTO
e _RP ² + e _RS ² + e _Rf ² + e_V ² + ( R _P + R _S ) ² i _p ² + R _f ² i _p ²
The noise from resistors can be calculated from the equation:
e _R = 4 × ^R nV/ Hz ^{at 25°C}
1000
where R is in Ω.
eRP = 2.2 nV/√Hz
eRS =eRf= 4 nV/√Hz
eV = 7 nV/√Hz
ip = iN = 1 pA/√Hz
eVAD8065 = 10 nV/√Hz
The Noise of the AD8475Attenuation Stage
The eAD8065_RTO term is the noise from the circuit at the input to
AD8475 stage. This noise is reflected to the output of the
AD8475 by multiplying the signal gain (0.4) of AD8475 stage as
shown in Figure 14.
e_{AD8065_R TO}
e_{AD8065_R TO}
e_{AD8475_R TO}
+
V_N
AD8475
–
V_P
Figure 14. AD8475 Noise Model
The AD8475 output voltage noise is also 10 nV/√Hz, including
amplifier voltage and current noise, as well as noise of internal
resistors.
The noise density of the whole signal chain in front of ADC is
( ) e = _{TOTAL _ GAIN}
2 × GAIN _AD8475 × e _{AD8475_RTO}
+ e ²
2
AD8475_RTO
For the ±10 V input range, the GAINAD8475 = 0.4.
eTOTAL_0.4 = 11.5 nV/√Hz
For the ±5 V input range, the GAINAD8475 = 0.8.
eTOTAL_0.8 = 15.1 nV/√Hz
The total output noise of the AD8475 is applied to the RC filter
(10 Ω, 2.2 nF) that has a bandwidth of 7.23 MHz. The
bandwidth of the AD8065 is 145 MHz, and the bandwidth of
the AD8475 is 150 MHz. The input bandwidth of the AD7984
ADC is 10 MHz, therefore the noise at the input of the AD7984
is limited by the RC noise filter to 7.23 MHz.
When the AD8475 is operating at a gain of 0.8 (worst case noise
condition) the input rms noise to the ADC is therefore
V _{TOTAL _ RMS} = (15.1nV/ Hz × 1.57 × 7.23 MHz = 51 μV
VTOTAL_PP = 6.6 × 51 µV = 337 µV
For the 18-bit AD7984 with reference voltage of 4.096 V, the
differential input span is 8.196 V. The LSB value is 31 µV. The
peak-to-peak noise of 337 µV therefore corresponds to 11 LSBs
peak-to-peak.
Effect of Multiplexer Switching Transients
The multiplexer has source and drain capacitance. The drain
capacitance of the multiplexer holds the voltage of previous
input channel. When the multiplexer switches to the next
channel, this can create a transient or kick-back glitch through
the RON resistance. This transient can affect the next conversion.
Therefore, the pre-filter driver needs to have a very low output
impedance and a fast settling time to the transient.
+10V ^PRE-FILTER P1
ADG5208
ADG5236
AI 1
–10V
AI 2
R_P
C_P
R_P ^VSS
C_P
C_S
V_SS
C_S
SW1
R_ON
SW2
R_ON
D
RON
C_D
C_S
C_D
V_SS
P3 _VSS
V_SS
V_SS
P2 V_SS
R_S
C_IN
P3
KICK
P2
P1
SW_A0
BACK-CHARGE
FORWARD-CHARGE
Figure 15. Multiplexer Switching Transients
The driver needs to be able to charge the input to the required
accuracy (forward-charge) before the switch opens. The back-
charge occurs when the switch opens, and generally is short and
doesn’t present a problem.
In order to make the circuit easy to drive, a buffer can be placed
in front of the multiplexer (front buffer). The evaluation board
EVAL-CN0269-SDPZ has footprints for the input buffer on
each input channel and has an AD8065 installed in Channel 1
to Channel 4. Adding the buffer slightly increases the noise
density and the settling time. However, in a practical application,
the parasitic inductance and capacitance from the input cable
or terminal connector will significantly increase the time of
settling time and generate ringing due to the forward and back
charge without the buffer. The additional input buffer isolates
the parasitic effects and provides very low impedance to the
multiplexer. The difference in performance between the circuit
with or without input buffer is shown in the test part of this
circuit note.
Another reason for adding the input buffer is for that an
additional filter can be placed ahead of it for anti-aliasing and
noise reduction.
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