CN0269 Datasheet, PDF (3/12 Pages) Analog Devices – Devices Connected

Circuit Note
CN-0269
Digital Delay
In the circuit shown in Figure 1, the ADC and multiplexer are
both triggered by the rising edge of CNV signal from digital
controller. At this point, the SAR ADC has completed the
acquisition of the sample and starts the conversion cycle.
Ideally, the signal chain has one full sampling period to settle to
the next channel, but there are delays in the digital circuits that
decrease the available settling time. In Figure 2, tDD is the sum of
the delay through the NAND gate and the counter CLK-to-
OUT delay. This digital delay can be found from the data sheet
of each component, and is approximately 8 ns total.
The time shown as tMD in Figure 2 is the delay through the two
stage multiplexer measured from the 50% point of the digital
input to the point that the analog output signal starts to settle.
Since the ADG5208 and ADG5236 are switched simultaneously
in this circuit, the tMD marked in Figure 2 is equal to the delay
generated by the slower one, which is the ADG5208.
The transition time delay of multiplexer is easy to find in the
data sheet. However, the transition delay on the data sheet is the
delay time between the 50% of the digital input and the 90%
point of the digital output as shown in Figure 3.
3V
ADDRESS
DRIVE (V_IN)
0V
t_MD
t_TRANSITION
OUTPUT
50%
50%
t_r < 20ns
t_f < 20ns
V_IN
t_TRANSITION
90%
90%
So tMD is calculated using the equation:
t = t − t MD TRANSITION SETTLE (90%)
(1)
The maximum settling time left for analog signal chain at a
sampling rate of 𝑓_𝑠 can be estimated by the equation:
tSETTLE(fs) = 1/fS – tDD − tMD
(2)
A good first order approximation for estimating multiplexer
settling time is to treat the multiplexer in the on state as a
simple RC circuit with time constant of RON × CD.
The time for switch to settle to within a % error can be
calculated by the equation below. See the AN-1024 Application
Note, “How to Calculate the Settling Time and Sampling Rate of
a Multiplexer” for more details.
The test circuit for measuring the transition delay with a load of
300 Ω||35 pF is shown in Figure 3. Under this test configuration,
the settling time can be estimated by Equation 3.
t _SETTLE
=
–
ln

% error
100




R _ON R _L
R _ON + R _L



(
C
D

+C_L
)
(3)
50Ω
2.0V
V_DD
V_SS
V_DD
V_SS
A0
S1
V_S1
A1
S2 TO S7
A2
S8
ADG5208
EN
D
V_S8
OUTPUT
GND
300Ω
35pF
Figure 3. ADG5208 Transition Delay Test Circuit
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