CN0269 Datasheet, PDF (7/12 Pages) Analog Devices – Devices Connected

Circuit Note
During the conversion phase, the switch is open and the REXT
and CEXT time constant determines the input settling time.
When the switch is closed and the ADC enters the acquisition
phase, the internal RIN and CIN is connected in parallel with the
external network, and a charge transient can be injected onto
the input.
In this circuit, with a 0.4× gain of the AD8475 and a 20 V
single-ended input step, the voltage step into the AD7984 is 4 V
single-ended and 8 V differential.
When the step voltage is initially applied, the AD8475 is in the
conversion mode, and the switch is open. The REXT and CEXT
time constant is 22 ns, and 12.48 time constants is 275 ns (time
required to settle to 18 bits shown in Table 1), which is less than
the 500 ns allowable conversion time when sampling at 1 MSPS.
When the AD7984 enters the acquisition mode at the end of the
500 ns interval, the switch closes. At this point, the voltage at the
RC filter input can be positive full-scale, and the voltage on CIN
can be negative full-scale, or vice-versa. The settling time of the
voltage across CIN is now a function of REXT, CEXT, RIN, and CIN.
The settling time for this circuit can be simulated by the Multisim
and is shown in Figure 11. The SIN is a component of Multisim
named PULSE_VOLTAGE which provides the 4 V step input with
50% duty cycle. Another PULSE_VOLTAGE in Figure 11 is
SW_ADC. This PULSE_VOLTAGE combined with ideal switch
A1 controls the CONVERSION and ACQUISITION cycle
timing of the SAR ADC. The pulse is 500 ns wide which equals
the CONVERSION time of the AD7984. The 5 μs is the half-
period of the input switching signal. The SIN and SW_ADC are
controlled by the same phase of the clock. The switch A1 is
open during the first 500 ns after SIN is switched. Switch A1
then closes, allowing the capacitive DAC to acquire the input
signal from the external RC filter.
XSC1
G
T
ABC D
SIN
0.5V, 4.5V
5µs, 10µs
RC FILTER
R_EXT
10Ω
C_EXT
2.2nF
U1
NOT
ADCINPUT
A1
R_IN
400Ω
4.5V, 0.5V
SW_ADC
0V, 5V
500ns, 5µs
C_IN
30pF
Figure 11. Multisim Settling Time Model of the AD7984 Front End
The simulation result is shown in Figure 12. The blue label
shows that the voltage on CIN settled to 4 V with 18-bit accuracy
469 ns after the input step signal. Therefore the total settling
time of the front end of the AD7984 is tSRC = 469 ns.
1
2
(11.0469µ 4)
CN-0269
OUT
RC_EXT
SW_ADC
SIN
9
10
11
12
13
14
15
16
TIME (µs)
Figure 12. Settling Time Waveforms for AD7984 Front End Simulation Model
Table 1 is useful and shows the number of time constants
required to settle to a given accuracy for a simple RC network.
Table 1. Number of Time Constants Required to Settle to a
Given Accuracy for an Simple RC Network
Resolution,
No. of Bits
No. of Time Constants =
LSB (%FS) −In (%Error/100)
6
1.563
4.16
8
0.391
5.55
10
0.0977
6.93
12
0.0244
8.32
14
0.0061
9.70
16
0.00153
11.09
18
0.00038
12.48
20
0.000095 13.86
22
0.000024 15.25
The total settling time of the entire circuit shown in Figure 1
can now be estimated:
t _{S _ ALL} 
t2
S _ MUX
 t _{S _ BUF} ²
 t _{S _ ATN} ²
 t _{S _ RC} ²
 2129 ²  600 ²  200 ²  469 ²  2270 ns
Therefore for settling to 18 bits, the maximum switching rate of
this circuit is:
fS < 1/(2270 ns + 147 ns) = 414 kHz
Noise Analysis
The Noise of the AD8065 Buffer Stage
The noise sources in the signal chain of this circuit are the
thermal noise from resistors and the voltage and current noise
from the AD8065 and the AD8475. The on resistance of the two
switches is small enough to ignore.
A simplified noise analysis model for the AD8065 circuit is
shown in Figure 13.
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