CN0269 Datasheet, PDF (4/12 Pages) Analog Devices – Devices Connected

CN-0269
Circuit Note
For the ADG5208, RON is 160 Ω, and CD is 52 pF. The transition
delay of ADG5208 is 160 ns. So, the 90% settling time of the
ADG5208 is
t _{SETTLE ( 90%)} = – ln _{} ¹⁰ _{} (160 || 300 Ω )(52 pF + 35 pF ) = 21 ns
 100 
From Equation 1,
tMD = tTRANSITION – tSETTLE(90%) = 160 ns – 21 ns = 139 ns
Therefore, under this circuit configuration with the ADG5208
and the ADG5236, the total extra time delay due to the digital
circuits is
tDD + tMD = 8 ns + 139 ns = 147 ns
CNV
t_AHEAD
t_CONV
Actually, this digital delay of 147 ns due to the digital control
circuit and part of the transition delay from multiplexer can be
compensated by delaying the rising edge of the convert signal
with respect to the multiplexer update signal by an amount of
time equal to tDD + tMD. However, both tDD and tMD are a function
of temperature, power supply voltage, and normal variations
from part to part. The time margin must be enough to account
for the variation and drift. For example, under this configuration
with 147 ns digital delay, switching the multiplexer 100 ns to
120 ns ahead of the ADC convert signal (tAHEAD) increases the
available settling time by the same amount.
The optimized timing is shown in Figure 4, but was not
implemented in the actual circuit in order to minimize
complexity.
t_S
t_ACQ
STATUS
CONVERSION
ACQUISITION
MUX CTRL
[CH3:CH0] ^[0000]
[0001]
VOUT_SW
TO CH0
t_DD t_MD
SETTLING TO CH1
t_SETTLE
Figure 4. Optimized Timing of Multichannel Data Acquisition Circuit
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