CN0269 Datasheet, PDF(5/12 Page) Analog Devices

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CN0269 Datasheet, PDF (5/12 Pages) Analog Devices – Devices Connected

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Circuit Note

Settling Time Analysis

When the circuit shown in Figure 1 is operating in the

continuous switching mode, all the 16-channel signal-ended or

8-channel differential signal streams are merged into a time-

division multiplexed signal by the two stage multiplexer, the

ADG5208 and ADG5236. The signal is then buffered by the

AD8065 that has a high impedance, low capacitance input.

Then the low impedance output of AD8065 buffer drives the

AD8475 stage that attenuates, level shifts, and performs the

single-ended to differential conversion. An RC (10 â¦, 2.2 nF)

filter is placed at the input of the AD7984 ADC in order to limit

out-of-band noise and attenuate the kickback from the switched

capacitor input of the ADC. The â3 dB bandwidth of the filter

is 7.2 MHz. (See Front-End Amplifier and RC Filter Design for a

Precision SAR Analog-to-Digital Converters, Analog Dialogue

46-12, December 2012).

For the purposes of calculating settling time, the circuit can be

divided into four parts as shown in Figure 5.

PART 1

MUX

ADG5208

ADG5236

PART 2

BUFFER

AD8065

PART 3

ATTENUATION

PART 4

RC + ADC

AD8475

AD7984

tS_MUX

tS_BUF

tS_ATN

tS_RC

Figure 5. Sub-Stage Block Diagram for Settling Time Analysis

Then the total settling time is estimated to be the root sum

square (rss) of settling time of each stage

t S _ ALL = t S _ MUX 2 + t S _ BUF 2 + t S _ ATN 2 + t S _ RC 2

In order to settle to within a specific error band at a sampling

rate, fS , the relationship below must be satisfied.

tS_ALL + tDD + tMD < 1/fS

Or, fS <1/(tS_ALL + tDD + tMD)

CN-0269

Settling Time for the Multiplexer Stage

The equivalent circuit for a CMOS switch can be approximated

as an ideal switch in series with a resistor (RON) and in parallel

with two capacitors (CS, CD). The multiplexer stage and

associated filters can therefore be modeled as shown in Figure 6.

PRE-FILTER

AI 1

AI 2

RPVSS

VSS

ADG5208

RON SW1

VSS RON SW2

VSS

ADG5236

RON

VSS

AD8065

CIN

VSS

Figure 6. First-Order Model for Input Pre-Filter, Multiplexer, and AD8065 Input

Note that the ADG5236 model does not show the series switch

because it only switches when changing from single-ended to

differential mode inputs.

The pre-filter in front of multiplexer is not shown in Figure 1.

This pre-filter is used for noise suppression. Also, the RP resistor

combined with protection diodes and the TVS provides

additional transient and over-voltage protection for hostile

environments. The protection components are shown in the

complete circuit schematic contained in the CN-0269 Design

Support Package.

The RS is the 1 kâ¦ resistor in series with non-inverting input of

the AD8065, and CIN is the input capacitance of AD8065. The

input impedance of AD8065 is 1 GÎ©||2.2 pF, and the 1 GÎ©

resistance can be ignored.

The circuit in Figure 6 was simulated using NI Multisimâ¢ as

shown in Figure 7, with the following component values:

Pre-filter: RP = 300 Î©; CP = 120 pF;

ADG5208: RON =160 Î©; CS = 5.5 pF; CD = 52 pF;

ADG5236: RON =160 Î©; CS = 2.5 pF; CD = 12 pF;

AD8065: RS =1 kÎ©; CIN = 2.2 pF;

XSC1

ABC D

259kHz

FIRST

RP1

300Î©

CP1

CA1

10V

120pF

10pF

â10V

RP2

300Î©

CP2

120pF

CA2

10pF

SECOND

CS1

5.5pF

CS2

5.5pF

RON1

160Î©

SW1

RON2

160Î©

SW2

ADG5208

ADG5236

THIRD

RON3

160Î©

CD1

52pF

CS3

2.5pF

CD2

15pF

FOURTH

1kÎ©

CIN

2.2pF

Figure 7. NI Multisim Simulation Circuit for the Pre-Filter, Multiplexer, and AD8065 Input

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