CN0269 Datasheet, PDF (6/12 Pages) Analog Devices – Devices Connected

Circuit Note
CN-0269
The simulation result is shown in Figure 8. From the simulation
result, the settling of the circuit shown in Figure 7 is:
tS_MUX = 10.1300 – 8.0011 = 2.129 µs
1
28.0
2
OUTPUT
23.6
(10.13µ 10)
19.1
14.7
10.3
(8.0011µ –10)
5.9
MUX_CTRL
1.5
–2.9
7
8
9
10
11
12
13
TIME (µs)
Figure 8. Pre-Filter, Multiplexer, and AD8065 Input Settling Time Simulation
Because the multiplexer settling time is 2.1 µs, this will limit the
maximum throughput rate per channel to 476 kSPS (1/2.1 µs),
even if the multiplexer was the only element in the signal chain.
Since the settling time contributions of each stage in the signal
chain add on an rss basis, stages having settling times of less
than approximately 2.1 µs ÷ 3 = 700 ns will have a minimum
effect on the total settling time.
Settling Time for AD8065 Buffer and AD8475
Attenuation Stages
The settling time of an amplifier is defined as the time it takes the
output to respond to a step change at the input and come into and
remain within a defined error band, as measured relative to the
50% point of the input pulse, as shown in Figure 9.
ERROR
BAND
DEAD SLEW RECOVERY
TIME TIME
TIME
FINAL
SETTLING
SETTLING TIME
Figure 9. Settling Time of an Op Amp
The error band is usually defined to be a specific percentage of the
step, such as 0.1%, 0.01%, 0.001%, etc. As shown in Figure 9, the
dead time, slew time, and recovery time together constitute the
total settling time.
For a high speed fast settling op amp, such as AD8065, the dead
time is only a small percentage of the total settling time and can
usually be ignored.
Op amp settling time is nonlinear; it may take 30 times as long
to settle to 0.01% as to 0.1%. Thermal effects within the op amp
can cause the op amp to take hundreds of microseconds to settle to
0.01%, although 0.1% settling may be less than 100 ns. Some op
amps that have a settling time specified to 0.1% may never settle
to 0.01% or 0.001% due to low amplitude ringing and/or long
term thermal effects.
Settling time is also a function of the op amp closed-loop gain and
the feedback network, as well as the compensation. Settling time
depends on the amplitude of the output voltage step. A large
output step generally has a longer settling time than a small one.
Measuring 0.01% or 0.001% settling time for a 10 V or 20 V output
step is an extremely difficult task due to the effects of oscilloscope
overdrive, sensitivity, and the difficulty of generating an input pulse
that settles to the required accuracy.
The AD8065 op amp has a 0.1% settling time specification of
250 ns for a 10 V output step and a slew rate of 180 V/µs. The
slew time for the output to swing 10 V is approximately 55 ns,
and the slew time for a 20 V output step is approximately
110 ns. We can estimate the 0.1 % settling time for a 20 V step
by adding the additional slew time to the specification for a
10 V step, and obtain approximately 250 ns + 55 ns = 305 ns.
Based on empirical data, we will assume the 0.01% settling time
is approximately 600 ns for a 20 V output step.
The AD8475 differential attenuating amplifier has a settling
time specification of 50 ns to 0.0001%, and a slew rate of
50 V/µs for a 2 V output step. In the circuit, the output is 8 V, so
assuming that the settling time is proportional to the output
voltage step, the 8 V settling time will be approximately 200 ns.
Settling Time for the Noise Filter and the AD7984 ADC
The AD7984 ADC is a member of the PulSAR® family and is
based on a charge-redistribution digital-to-analog converter
capacitive DAC. The output code is determined in two phases.
The first phase is the acquisition phase. The internal capacitive
DAC is switched to the ADC input pins in order to acquire the
signal. The external support circuitry driving the ADC input
must be able to settle to the required voltage at the end of
acquisition phase. The ADC then enters the conversion phase,
and the capacitive DAC is disconnected from the input. The
conversion is then performed during this phase using the SAR
conversion algorithm.
The equivalent analog input circuit combined with the external
RC filter is shown in Figure 10. The REXT and CEXT are the
external filter in front of the ADC, which is 10 Ω and 2.2 nF in
this circuit. The pin capacitance (CPIN) of several pF can be
ignored because of the large CEXT.The value of RIN is typically
400 Ω, and CIN is typically 30 pF.
REF
AD7984
R_EXT
D1
IN+ OR IN–
C_EXT
C_PIN
D2
R_IN
C_IN
GND
GND
GND
Figure 10. AD7984 Input Equivalent Circuit
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