ADSP-BF526_15 Datasheet, PDF (62/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Timer Cycle Timing
Table 53 and Figure 31 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f_SCLK/2) MHz.
Table 53. Timer Cycle Timing
ADSP-BF522/ADSP-BF524/ADSP-BF526 ADSP-BF523/ADSP-BF525/ADSP-BF527
V_DDEXT
1.8V Nominal
V_DDEXT
2.5 V or 3.3V Nominal
V_DDEXT
1.8V Nominal
V_DDEXT
2.5 V or 3.3V Nominal
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Timing Requirements
t_WL
Timer Pulse Width Input t_SCLK
t_SCLK
t_SCLK
t_SCLK
ns
Low (Measured In SCLK
Cycles)¹
t_WH
Timer Pulse Width Input t_SCLK
t_SCLK
t_SCLK
t_SCLK
ns
High (Measured In SCLK
Cycles)¹
t_TIS
Timer Input Setup Time 10
7
Before CLKOUT Low²
8.1
6.2
ns
t_TIH
Timer Input Hold Time –2
–2
–2
–2
ns
After CLKOUT Low²
Switching Characteristics
t_HTO
Timer Pulse Width Output t_SCLK –1.5
(Measured In SCLK Cycles)
(2³²â€“ 1)t_SCLK t_SCLK – 1
(2³²â€“ 1)t_SCLK t_SCLK – 1
(2³²â€“ 1)t_SCLK t_SCLK – 1
(2³² – 1)t_SCLK ns
t_TOD
Timer Output Update
6
6
6
6
ns
Delay After CLKOUT High
1 _{The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.}
2 _{Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.}
CLKOUT
TMRx OUTPUT
TMRx INPUT
t_TOD
t_TIS
t_TIH
t_HTO
t_WH,t_WL
Figure 31. Timer Cycle Timing
Rev. D | Page 62 of 88 | July 2013