ADSP-BF526_15 Datasheet, PDF (24/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Table 10. Signal Descriptions (Continued)
Signal Name
USB 2.0 HS OTG
USB_DP
USB_DM
USB_XI
USB_XO
USB_ID
USB_VREF
USB_RSET
USB_VBUS
Port F: GPIO and Multiplexed Peripherals
PF0/PPI D0/DR0PRI /ND_D0A
PF1/PPI D1/RFS0/ND_D1A
PF2/PPI D2/RSCLK0/ND_D2A
PF3/PPI D3/DT0PRI/ND_D3A
PF4/PPI D4/TFS0/ND_D4A/TACLK0
PF5/PPI D5/TSCLK0/ND_D5A/TACLK1
PF6/PPI D6/DT0SEC/ND_D6A/TACI0
PF7/PPI D7/DR0SEC/ND_D7A/TACI1
PF8/PPI D8/DR1PRI
PF9/PPI D9/RSCLK1/SPISEL6
PF10/PPI D10/RFS1/SPISEL7
PF11/PPI D11/TFS1/CZM
PF12/PPI D12/DT1PRI/SPISEL2/CDG
PF13/PPI D13/TSCLK1/SPISEL3/CUD
PF14/PPI D14/DT1SEC/UART1TX
PF15/PPI D15/DR1SEC/UART1RX/TACI3
Type Function
Driver
Type¹
I/O Data + (This ball should be pulled low when USB is unused or not present.) F
I/O Data – (This ball should be pulled low when USB is unused or not present.) F
I
USB Crystal Input (This ball should be pulled low when USB is unused or not
present.)
O USB Crystal Output (This ball should be left unconnected when USB is unused F
or not present.)
I
USB OTG mode (This ball should be pulled low when USB is unused or not
present.)
A USB voltage reference (Connect to GND through a 0.1 μF capacitor or leave
unconnected when not used.)
A USB resistance set. (This ball should be left unconnected.)
I/O 5V USB VBUS. USB_VBUS is an output only in peripheral mode during SRP F
signaling. Host mode requires that an external voltage source of 5 V at 8 mA
or more (per the OTG specification) be applied to VBUS. The voltage source
needs to be able to charge and discharge VBUS, thus an ON/OFF switch is
required to control the voltage source. A GPIO can be used for this purpose
(This ball should be pulled low when USB is unused or not present.)
I/O GPIO/PPI Data 0/SPORT0 Primary Receive Data
C
/NAND Alternate Data 0
I/O GPIO/PPI Data 1/SPORT0 Receive Frame Sync
C
/NAND Alternate Data 1
I/O GPIO/PPI Data 2/SPORT0 Receive Serial Clock
D
/NAND Alternate Data 2/Alternate Capture Input 0
I/O GPIO/PPI Data 3/SPORT0 Transmit Primary Data
C
/NAND Alternate Data 3
I/O GPIO/PPI Data 4/SPORT0 Transmit Frame Sync
C
/NAND Alternate Data 4/Alternate Timer Clock 0
I/O GPIO/PPI Data 5/SPORT0 Transmit Serial Clock
D
/NAND Alternate Data 5/Alternate Timer Clock 1
I/O GPIO/PPI Data 6/SPORT0 Transmit Secondary Data
C
/NAND Alternate Data 6/Alternate Capture Input 0
I/O GPIO/PPI Data 7/SPORT0 Receive Secondary Data
C
/NAND Alternate Data 7/Alternate Capture Input 1
I/O GPIO/PPI Data 8/SPORT1 Primary Receive Data
C
I/O GPIO/PPI Data 9/SPORT1 Receive Serial Clock/SPI Slave Select 6
D
I/O GPIO/PPI Data 10/SPORT1 Receive Frame Sync/SPI Slave Select 7
C
I/O GPIO/PPI Data 11/SPORT1 Transmit Frame Sync/Counter Zero Marker
C
I/O GPIO/PPI Data 12/SPORT1 Transmit Primary Data/SPI Slave Select 2/Counter C
Down Gate
I/O GPIO/PPI Data 13/SPORT1 Transmit Serial Clock/SPI Slave Select 3/Counter Up D
Direction
I/O GPIO/PPI Data 14/SPORT1 Transmit Secondary Data/UART1 Transmit
C
I/O GPIO/PPI Data 15/SPORT1 Receive Secondary Data
C
/UART1 Receive /Alternate Capture Input 3
Rev. D | Page 24 of 88 | July 2013