ADSP-BF526_15 Datasheet, PDF (49/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
External DMA Request Timing
Table 39, Table 40, and Figure 19 describe the External DMA
Request operations.
Table 39. External DMA Request Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors¹
V_DDEXT/V_DDMEM
1.8 V Nominal
V_DDEXT/V_DDMEM
2.5 V or 3.3 V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t_DS
DMARx Asserted to CLKOUT High Setup
9.0
6.0
ns
t_DH
CLKOUT High to DMARx Deasserted Hold Time
0.0
0.0
ns
t_DMARACT
DMARx Active Pulse Width
1.0 × t_SCLK
1.0 × t_SCLK
ns
t_DMARINACT
DMARx Inactive Pulse Width
1.75 × t_SCLK
1.75 × t_SCLK
ns
1 _{Because the external DMA control pins are part of the VDDEXT power domain and the CLKOUT signal is part of the VDDMEM power domain, systems in which VDDEXT and}
V_DDMEM are NOT equal may require level shifting logic for correct operation.
Table 40. External DMA Request Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors¹
V_DDEXT/V_DDMEM
1.8 V Nominal
V_DDEXT/V_DDMEM
2.5 V or 3.3 V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t_DS
DMARx Asserted to CLKOUT High Setup
8.0
6.0
ns
t_DH
CLKOUT High to DMARx Deasserted Hold Time
0.0
0.0
ns
t_DMARACT
DMARx Active Pulse Width
1.0 × t_SCLK
1.0 × t_SCLK
ns
t_DMARINACT
DMARx Inactive Pulse Width
1.75 × t_SCLK
1.75 × t_SCLK
ns
1 _{Because the external DMA control pins are part of the VDDEXT power domain and the CLKOUT signal is part of the VDDMEM power domain, systems in which VDDEXT and}
V_DDMEM are NOT equal may require level shifting logic for correct operation.
CLKOUT
DMAR0/1
(ACTIVE LOW)
DMAR0/1
(ACTIVE HIGH)
t_DS
t_DH
t_DMARACT
t_DMARINACT
Figure 19. External DMA Request Timing
Rev. D | Page 49 of 88 | July 2013