ADSP-BF526_15 Datasheet, PDF (29/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Table 11 shows settings for TWI_DT in the NONGPIO_DRIVE
register. Set this register prior to using the TWI port.
Table 11. TWI_DT Field Selections and V_DDEXT/V_BUSTWI
TWI_DT
000 (default)¹
V_DDEXT Nominal
3.3
V_BUSTWI Min
2.97
V_BUSTWI Nominal
3.3
V_BUSTWI Max
3.63
001
1.8
1.7
1.8
1.98
010
2.5
2.97
3.3
3.63
011
1.8
2.97
3.3
3.63
100
3.3
4.5
5
5.5
101
1.8
2.25
2.5
2.75
110
2.5
2.25
2.5
2.75
111 (reserved)
–
–
–
–
1 _{Designs must comply with the VDDEXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.}
Unit
V
V
V
V
V
V
V
–
Clock Related Operating Conditions
for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Table 12 describes the core clock timing requirements for the
ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Take care
in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the
maximum core clock and system clock (see Table 14). Table 13
describes phase-locked loop operating conditions.
Table 12. Core Clock (CCLK) Requirements (All Instruction Rates¹) for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Parameter
f_CCLK
Core Clock Frequency (V_DDINT =1.33 V minimum)
f_CCLK
Core Clock Frequency (V_DDINT = 1.235 V minimum)
1 _{See the Ordering Guide on Page 88.}
2 _{Applies to 400 MHz models only. See the Ordering Guide on Page 88.}
Nominal Voltage Setting Max
1.40 V
400²
1.30 V
300
Unit
MHz
MHz
Table 13. Phase-Locked Loop Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Parameter
Min
f_VCO
Voltage Controlled Oscillator (VCO) Frequency
70
1 _{See the Ordering Guide on Page 88.}
Max
Unit
Instruction Rate¹
MHz
Table 14. SCLK Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
V_DDEXT/V_DDMEM
1.8 V Nominal¹
V_DDEXT/V_DDMEM
2.5 V or 3.3 V Nominal
Parameter
Max
Max
f_SCLK
CLKOUT/SCLK Frequency (V_DDINT ≥ 1.33 V)²
80
100
f_SCLK
CLKOUT/SCLK Frequency (V_DDINT < 1.33 V)
80
80
1 _{If either VDDEXT or VDDMEM are operating at 1.8 V nominal, fSCLK is constrained to 80 MHz.}
2 _{fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 37 on Page 47.}
Unit
MHz
MHz
Rev. D | Page 29 of 88 | July 2013