ADSP-BF526_15 Datasheet, PDF (41/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Asynchronous Memory Read Cycle Timing
Table 34. Asynchronous Memory Read Cycle Timing
ADSP-BF522/ADSP-BF524/
ADSP-BF526
V_DDMEM
1.8 V Nominal
V_DDMEM
2.5 V or 3.3 V
Nominal
Parameter
Min Max Min
Max
Timing Requirements
t_SDAT
DATA15–0 Setup Before CLKOUT 2.1
2.1
t_HDAT
DATA15–0 Hold After CLKOUT
1.2
0.8
t_SARDY ARDY Setup Before CLKOUT
4.0
4.0
t_HARDY ARDY Hold After CLKOUT
0.2
0.2
Switching Characteristics
t_DO
Output Delay After CLKOUT¹
t_HO
Output Hold After CLKOUT¹
6.0
6.0
0.8
0.8
1 _{Output balls include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.}
ADSP-BF523/ADSP-BF525/
ADSP-BF527
V_DDMEM
1.8 V Nominal
V_DDMEM
2.5 V or 3.3 V
Nominal
Min Max Min
Max
2.1
2.1
0.9
0.8
4.0
4.0
0.2
0.2
6.0
6.0
0.8
0.8
Unit
ns
ns
ns
ns
ns
ns
CLKOUT
AMSx
SETUP
2 CYCLES
t_DO
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
HOLD
3 CYCLES
1 CYCLE
t_HO
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA 15–0
t_DO
t_SARDY
t_HO
t_HARDY
t_SARDY
t_HARDY
t_SDAT
t_HDAT
Figure 11. Asynchronous Memory Read Cycle Timing
Rev. D | Page 41 of 88 | July 2013