ADSP-BF526_15 Datasheet, PDF (58/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Serial Peripheral Interface (SPI) Port—Master Timing
Table 48 and Figure 28 describe SPI port master operations.
Table 48. Serial Peripheral Interface (SPI) Port—Master Timing
ADSP-BF522/ADSP-BF524/
ADSP-BF526
V_DDEXT
1.8V Nominal
V_DDEXT
2.5 V or 3.3V
Nominal
Parameter
Min
Max Min
Max
Timing Requirements
t_SSPIDM Data Input Valid to SCK Edge (Data 11.6
9.6
Input Setup)
t_HSPIDM SCK Sampling Edge to Data Input –1.5
–1.5
Invalid
Switching Characteristics
t_SDSCIM
t_SPICHM
t_SPICLM
t_SPICLK
t_HDSM
t_SPITDM
t_DDSPIDM
SPISELx low to First SCK Edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISELx High
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data
Out Delay)
2 × t_SCLK – 1.5
2 × t_SCLK – 1.5
2 × t_SCLK – 1.5
4 × t_SCLK – 1.5
2 × t_SCLK – 1.5
2 × t_SCLK – 1.5
6
2 × t_SCLK –1.5
2 × t_SCLK –1.5
2 × t_SCLK –1.5
4 × t_SCLK – 1.5
2 × t_SCLK –1.5
2 × t_SCLK –1.5
6
t_HDSPIDM SCK Edge to Data Out Invalid (Data –1.0
–1.0
Out Hold)
ADSP-BF523/ADSP-BF525/
ADSP-BF527
V_DDEXT
1.8V Nominal
V_DDEXT
2.5 V or 3.3V
Nominal
Min
Max Min
Max
11.6
9.6
–1.5
–1.5
2 × t_SCLK –1.5
2 × t_SCLK –1.5
2 × t_SCLK –1.5
4 × t_SCLK – 1.5
2 × t_SCLK –1.5
2 × t_SCLK –1.5
6
–1.0
2 × t_SCLK –1.5
2 × t_SCLK –1.5
2 × t_SCLK –1.5
4 × t_SCLK – 1.5
2 × t_SCLK –1.5
2 × t_SCLK –1.5
6
–1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPIxSELy
(OUTPUT)
SPIxSCK
(OUTPUT)
t_SDSCIM
t_SPICLM
t_SPICHM
t_SPICLK
t_HDSM
t_SPITDM
SPIxMOSI
(OUTPUT)
CPHA = 1
SPIxMISO
(INPUT)
t_HDSPIDM
t_DDSPIDM
t_SSPIDM
t_HSPIDM
SPIxMOSI
(OUTPUT)
CPHA = 0
t_SSPIDM
SPIxMISO
(INPUT)
t_HSPIDM
t_HDSPIDM
t_DDSPIDM
Figure 28. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. D | Page 58 of 88 | July 2013