AD9510_15 Datasheet, PDF (50/56 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

AD9510
Data Sheet
Reg.
Addr.
(Hex) Bit(s) Name
Description
3C [7:4]
Not used.
3D
3E
3F
40 [0] Power-down
Power-down bit for both output and LVDS driver. 0 = LVDS/CMOS on (default), 1 = LVDS/CMOS power-down.
41
LVDS/CMOS
42
OUT4
43
OUT5
OUT6
OUT7
40 [2:1] Output current
level
41
LVDS
42
OUT4
43
OUT5
OUT6
OUT7
[2]
[1]
Current (mA)
Termination (Ω)
0
0
1.75
100
0
1
3.5 (default)
100
1
0
5.25
50
1
1
7
50
40 [3] LVDS/CMOS select 0 = LVDS (default), 1 = CMOS.
41
OUT4
42
OUT5
43
OUT6
OUT7
[4] Inverted CMOS
driver
Effects output only when in CMOS mode.
0 = disable inverted CMOS driver (default), 1 = enable inverted CMOS driver.
40
OUT4
41
OUT5
42
OUT6
43
OUT7
40 [7:5]
Not used.
41
42
43
44 [7:0]
Not used.
45 [0] Clock select
0: CLK2 drives distribution section, 1: CLK1 drives distribution section (default).
45 [1] CLK1 power-down 1 = CLK1 input is powered down (default = 0b).
45 [2] CLK2 power-down 1 = CLK2 input is powered down (default = 0b).
45 [3] Prescaler clock
power-down
1 = shut down clock signal to PLL prescaler (default = 0b).
45 [4] REFIN power-down 1 = power-down REFIN (default = 0b).
45 [5] All clock inputs
power-down
1 = power-down CLK1 and CLK2 inputs and associated bias and internal clock tree (default = 0b).
45 [7:6]
Not used.
46 [7:0]
Not used.
47 [7:0]
Not used.
Rev. B | Page 50 of 56