AD9510_15 Datasheet, PDF (47/56 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Data Sheet
AD9510
Reg.
Addr.
(Hex) Bit(s) Name
08 [5:2] PLL mux control
08 [6] Phase frequency
detector (PFD)
polarity
08 [7]
09 [0] Reset all counters
09 [1] N-counter reset
09 [2] R-counter reset
09 [3]
09 [6:4] Charge pump (CP)
current setting
09 [7]
0A [1:0] PLL power-down
Description
[5]
[4] [3] [2] MUXOUT—Signal on STATUS Pin
0
0
00
Off (signal goes low) (default)
0
0
01
Digital lock detect (active high)
0
0
10
N divider output
0
0
11
Digital lock detect (active low)
0
1
00
R divider output
0
1
01
Analog lock detect (N channel, open-drain)
0
1
10
A counter output
0
1
11
Prescaler output (NCLK)
1
0
00
PFD up pulse
1
0
01
PFD down pulse
1
0
10
Loss of reference (active high)
1
0
11
Tristate
1
1
00
Analog lock detect (P channel, open-drain)
1
1
01
Loss of reference or loss of lock (inverse of DLD) (active high)
1
1
10
Loss of reference or loss of lock (inverse of DLD) (active low)
1
1
11
Loss of reference (active low)
MUXOUT is the PLL portion of the STATUS output MUX.
0 = negative (default), 1 = positive.
Not used.
0 = normal (default), 1 = reset R, A, and B counters.
0 = normal (default), 1 = reset A and B counters.
0 = normal (default), 1 = reset R counter.
Not used.
[6]
[5]
[4]
ICP (mA)
0
0
0
0.60
0
0
1
1.2
0
1
0
1.8
0
1
1
2.4
1
0
0
3.0
1
0
1
3.6
1
1
0
4.2
1
1
1
4.8
Default = 000b.
These currents assume: CPRSET = 5.1 kΩ.
Actual current can be calculated by: CP_LSB = 3.06/CPRSET.
Not used.
01 = Asynchronous power-down (default).
[1]
[0]
Mode
0
0
Normal operation
0
1
Asynchronous power-down
1
0
Normal operation
1
1
Synchronous power-down
Rev. B | Page 47 of 56