AD9510_15 Datasheet, PDF (48/56 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

AD9510
Data Sheet
Reg.
Addr.
(Hex) Bit(s) Name
0A [4:2] Prescaler value
(P/P + 1)
0A [5]
0A [6] B counter bypass
Description
[4]
[3] [2]
Mode Prescaler Mode
0
0
0
FD
Divide by 1
0
0
1
FD
Divide by 2
0
1
0
DM
2/3
0
1
1
DM
4/5
1
0
0
DM
8/9
1
0
1
DM
16/17
1
1
0
DM
32/33
1
1
1
FD
Divide by 3
DM = dual modulus, FD = fixed divide.
Not used.
Only valid when operating the prescaler in fixed divide (FD) mode. When this bit is set, the B counter is
divided by 1. This allows the prescaler setting to determine the divide for the N divider.
0A [7]
Not used.
0B [5:0] 14-bit reference R divider MSB[13:8].
counter, R MSBs
0C [7:0] 14-bit reference R divider MSB[7:0].
counter, R LSBs
0D [1:0] Antibacklash pulse
width
[1]
[0]
Antibacklash Pulse Width (ns)
0
0
1.3 (default)
0
1
2.9
1
0
6.0
1
1
1.3
0D [4:2]
Not used
0D [5] Digital lock detect
window
[5]
Digital Lock Detect Window (ns) Digital Lock Detect Loss of Lock Threshold (ns)
0 (default) 9.5
15
1
3.5
7
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window
time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the
loss of lock threshold.
0D [6] Lock detect disable 0 = normal lock detect operation (default), 1 = disable lock detect.
0D [7]
Not used.
Unused
0E33
Not used.
Fine delay adjust
[0] Delay control
Delay block control bit.
34
OUT5
Bypasses delay block and powers it down (default = 1b).
38
OUT6
34 [7:1]
Not used.
38
Rev. B | Page 48 of 56