AD9510_15 Datasheet, PDF (1/56 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Data Sheet
1.2 GHz Clock Distribution IC, PLL Core,
Dividers, Delay Adjust, Eight Outputs
AD9510
FEATURES
Low phase noise phase-locked loop core
Reference input frequencies to 250 MHz
Programmable dual modulus prescaler
Programmable charge pump (CP) current
Separate CP supply (VCPS) extends tuning range
Two 1.6 GHz, differential clock inputs
8 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust
4 independent 1.2 GHz LVPECL outputs
Additive output jitter of 225 fs rms
4 independent 800 MHz low voltage differential signaling
(LVDS) or 250 MHz complementary metal oxide conductor
(CMOS) clock outputs
Additive output jitter of 275 fs rms
Fine delay adjust on 2 LVDS/CMOS outputs
Serial control port
Space-saving 64-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and
mixed-signal front ends (MxFEs)
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
GENERAL DESCRIPTION
The AD9510 provides a multi-output clock distribution function
along with an on-chip phase-locked loop (PLL) core. The design
emphasizes low jitter and phase noise to maximize data converter
performance. Other applications with demanding phase noise
and jitter requirements also benefit from this device.
The PLL section consists of a programmable reference divider
(R); a low noise, phase frequency detector (PFD); a precision
charge pump (CP); and a programmable feedback divider (N).
By connecting an external voltage-controlled crystal oscillator
(VCXO) or voltage-controlled oscillator (VCO) to the CLK2
and CLK2B pins, frequencies of up to 1.6 GHz can be synchronized
to the input reference.
There are eight independent clock outputs. Four outputs are low
voltage positive emitter-coupled logic (LVPECL) at 1.2 GHz,
and four are selectable as either LVDS (800 MHz) or CMOS
(250 MHz) levels.
REFIN
REFINB
FUNCTION
CLK1
CLK1B
SCLK
SDIO
SDO
CSB
FUNCTIONAL BLOCK DIAGRAM
VS GND
RSET
CPRSET VCP
DISTRIBUTION
REF
AD9510
SYNCB,
RESETB
PDB
R DIVIDER
N DIVIDER
PHASE
FREQUENCY
DETECTOR
PLL
REF
CHARGE
PUMP
PLL
SETTINGS
SERIAL
CONTROL
PORT
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST
/1, /2, /3... /31, /32
/1, /2, /3... /31, /32
/1, /2, /3... /31, /32
/1, /2, /3... /31, /32
/1, /2, /3... /31, /32
/1, /2, /3... /31, /32 ∆T
/1, /2, /3... /31, /32 ∆T
/1, /2, /3... /31, /32
LVPECL
LVPECL
LVPECL
LVPECL
LVDS/CMOS
LVDS/CMOS
LVDS/CMOS
LVDS/CMOS
CP
STATUS
CLK2
CLK2B
OUT0
OUT0B
OUT1
OUT1B
OUT2
OUT2B
OUT3
OUT3B
OUT4
OUT4B
OUT5
OUT5B
OUT6
OUT6B
OUT7
OUT7B
Figure 1.
Each output has a programmable divider that can be bypassed
or set to divide by any integer up to 32. The phase of one clock
output relative to another clock output can be varied by means
of a divider phase select function that serves as a coarse timing
adjustment. Two of the LVDS/CMOS outputs feature program-
mable delay elements with full-scale ranges up to 8 ns of delay.
This fine tuning delay block has 5-bit resolution, giving 25
possible delays from which to choose for each full-scale setting
(Register 0x36 and Register 0x3A = 00000b to 11000b).
The AD9510 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9510 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. An external VCO, which requires an
extended voltage range, can be accommodated by connecting
the charge pump supply (VCP) to 5.5 V. The temperature range
is −40°C to +85°C.
Rev. B
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