EVAL-AD1896EB Datasheet, PDF (5/28 Pages) Analog Devices – AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board

EVAL-AD1896EB
DEFAULT CONFIGURATION
The default configuration of this evaluation board is highlighted
in Tables VII and VIII. The AD1896 is configured in 24-bit
input and output data format, with input serial ports in slave
mode and output serial port in (768 Ï« f_S) master mode. In this
configuration, input serial port needs to be driven by an external
system, such as, Audio Precision, for the slave mode operation.
An on-board third overtone crystal oscillator at 33.8688 MHz
clocks the AD1896. Since the output serial port is configured
in 768 Ï« f_S master mode and the AD1896 is clocked by
33.8688 MHz clock, the output sample rate will be 44.1 kHz
for this configuration. The maximum input sample rate for this
case can be up to 192 kHz based on the requirement that the
AD1896 master clock must be higher than 138 times the
maximum input or output sample rate. The AD1896 can be
clocked by secondary on-board clock oscillator (U15) by first
inserting the desired clock oscillator in socket U15 and then
switching the clock source selection from on-board crystal to
clock oscillator (U15) by jumper JP4; however, clock oscillator is
enabled for SLAVE mode only (Switch S3 position 7). The evalua-
tion board contains 12.288 MHz (U15) clock oscillator. The
operating and quiescent currents for the ± 12 V dc supplies are
listed below.
+12 V Quiescent Current
–12 V Quiescent Current
+12 V Normal Operation Current
–12 V Normal Operation Current
~250 mA
~5 mA
~300 mA–360 mA
~5 mA
AP1 TRANSMITTER
SCLK
LRCLK
SDATA
AD1896
SCLK_I SCLK_O
LRCLK_I LRCLK_O
SDATA_I SDATA_O
AP2 RECEIVER
SCLK
LRCLK
SDATA
Figure 2. Input and Output Serial Port Direction in Default
Configuration
Input
Mode
(S3)
Position 0
LJ-24 Bits
Output
Mode
(JP1)
Position 1, 2, 3, 4
Shorted
LJ-24 Bits
Table VII. Default Jumper/Switch Settings
Master/Slave
Mode
(S4)
Position 6
Output Port
Master,
768 f_{S_OUT}
DAC
Interpolation
Ratio Select
(JP2)
Position 1, 2
Shorted
48 kHz
Sample
Rate
Clock
Source
(JP4)
Position 2, 3
Shorted
33.8688 MHz
Crystal
Oscillator
Group
Delay
(S8)
Pushed Up
Short
Bypass
Mode
(S6)
Pushed
Down
Off
Mute
(S7)
Pushed
Down
Off
Table VIII. Default Evaluation Board Configuration
Input
Output Master/Slave
Mode (S3) Mode (JP1) Mode (S4)
LJ X LJ-24 X Both Ports in
SLAVE Mode
I²S
I²S-24
O_MAS_768 X
RJ-24
RJ-24
O_MAS_512
Input Source
(HDR3, HDR1,
J1, U4)
DIRECT
X
INPUT
TDM_IN
SPDIF
Output Source
(HDR2, HDR5,
J2)
SPDIF
DIRECT X
OUTPUT
TDM_OUT
DAC
Interpolation
Ratio Select
(JP2)
96/48
X
192/48
X
Clock Source
(JP4)
On-Board
X
33.8688 MHz Crystal
External
256 Ï« f_S Clock
RJ-20
RJ-20
O_MAS_256
TOSLINK
RJ-18
RJ-18
MATCHED
PHASE
Group Delay
(S8)
Bypass Mode
(S6)
Automute
Mute
Enable (JP3) (S7)
RJ-16
RJ-16
I_MAS_768
Short
X Enable
Enable
X Enable
TDM
I_MAS_512
Long
Disable
X Disable
Disable
X
I_MAS_256
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