EVAL-AD1896EB Datasheet, PDF (26/28 Pages) Analog Devices – AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board

EVAL-AD1896EB
SCLK_DAC
= ISCLK;
FSYNC_DIT
SCLK_DIT
= ILRCLK;
= ((!ISCLK) & (LJ # RJ24 # RJ20 # RJ18 # RJ16)) # (ISCLK & I2S);
// Internal node signals
out_pld.abl
ISCLK = ((SCLK_O) & (O_MAS_768 # O_MAS_512 # O_MAS_256))
# ((DDO_SCLK) & (BOTH_SLAVE # MATCH_PHASE # IN_MAS_768 # IN_MAS_512 #
IN_MAS_256));
ILRCLK = ((LRCLK_O) & (O_MAS_768 # O_MAS_512 # O_MAS_256))
# ((DDO_LRCLK) & (BOTH_SLAVE#MATCH_PHASE#IN_MAS_768#IN_MAS_512#IN_MAS_256) & (LJ
# TDM # RJ24 # RJ20 # RJ18 # RJ16))
# ((!DDO_LRCLK) & (BOTH_SLAVE#MATCH_PHASE#IN_MAS_768#IN_MAS_512#IN_MAS_256) &
(I2S));
"====================================================================================
END IF_Logic
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