EVAL-AD1896EB Datasheet, PDF (22/28 Pages) Analog Devices – AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board

EVAL-AD1896EB
in_pld.abl
// IO control logic
DDI_SCLK.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256);
DDI_LRCLK.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256);
DIR_FSYNC.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256);
DIR_SCLK.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256);
SCLK_I.oe
= (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256);
LRCLK_I.oe = (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256);
DDI_SCLK
DDI_LRCLK
DIR_SCLK
DIR_FSYNC
= ISCLK;
= ILRCLK;
= ((!ISCLK) & (LJ # RJ24 # RJ20 # RJ18 # RJ16)) # (ISCLK & I2S);
= ILRCLK;
// AD1896 ASRC Input Serial port signals
SCLK_I
(SPDIF_DDI));
= ((LJ # RJ24 # RJ20 # RJ18 # RJ16 # I2S) & (ISCLK) & (!SPDIF_DDI))
# ((((LJ # RJ24 # RJ20) & (!ISCLK)) # ((I2S # RJ18 # RJ16) & (ISCLK))) &
LRCLK_I
(!SPDIF_DDI));
SDATA_I
(SPDIF_DDI));
= (SPDIF_DDI & DIR_FSYNC) # (((I2S & !DDI_LRCLK) # (!I2S & DDI_LRCLK)) &
= (DDI_SDATA & !SPDIF_DDI) # (((LJ#RJ24#RJ20#RJ18#RJ16#I2S)&(DIR_SDATA)) &
// Internal node signals
ISCLK = ((DDI_SCLK) & (BOTH_SLAVE#MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) &
(!SPDIF_DDI))
# ((LJ#RJ24#RJ20) & ((DIR_SCLK) &
(BOTH_SLAVE#MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) & (SPDIF_DDI)))
# ((SCLK_I) & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256))
# ((I2S # RJ18 # RJ16) & (DIR_SCLK) &
(BOTH_SLAVE#MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) & (SPDIF_DDI));
ILRCLK = ((DDI_LRCLK) & (BOTH_SLAVE # MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) &
(!SPDIF_DDI))
# ((DIR_FSYNC) & (BOTH_SLAVE # MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) &
(SPDIF_DDI))
# ((LRCLK_I) & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256));
I_SDATA = (DDI_SDATA & !SPDIF_DDI) # (DIR_SDATA & SPDIF_DDI);
"====================================================================================
END IF_Logic
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