EVAL-AD1896EB Datasheet, PDF (20/28 Pages) Analog Devices – AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board

EVAL-AD1896EB
in_pld.abl
MODULE IF_Logic
TITLE 'AD1896 EVB Input Interface Logic'
//===================================================================================
// FILE:
input_pld.abl
// REVISION DATE: 03-20-01
// REVISION BY:
Chirag Patel
// REVISION: 1.0
//
// DESCRIPTION:
//
// This input interface PLD (U2) selects between the External Data Interface header
// (HDR3) and the on-board CS8414 DIR (U1) for the AD1896 ASRC input signals, depending
// upon the SPDIF/DDI switch position (S1). When the SPDIF Receiver DIR is the selected
// signal source the digital audio signals, SDATA_I, SCLK_I and LRCLK_I are derived from
// the DIR output. SPDIF receiver needs the digital data in the SPDIF format in order to
// generate these signals. When the external data is the selected source the digital
// signals from (HDR3) are applied to the AD1896.
// Signals SCLK_I, LRCLK_I, DDI_SCLK, DDI_LRCLK, DIR_SCLK, DIR_FSYNC on the PLD are
// bi-directional signals. The direction of these signals are controlled by the
// MASTER_SLAVE MODE switch position (S4). When the AD1896 input serial port is set in the
// master mode, the SCLK_I and LRCLK_I are generated from the AD1896 input serial port.
// On the other hand, these signals are provided from the external source in the slave mode
// operation.
// PLD also decodes the Input Interface Format Switch (S3) and sets the Interface mode pins
// for both the CS8414 DIR and the AD1896 ASRC.
//===================================================================================
LIBRARY 'MACH';
DECLARATIONS
// IF_Logic DEVICE 'M4-64/32-15VC';
"INPUTS ===========================================================================
// TDI, TCK, TMS
pin 4,7,26 istype 'com';
//JTAG I/P's
DIR_SDATA
pin 1 istype 'com';
//CS8414 DIR SDATA OUT
SPDIF_DDI
pin 12 istype 'com';
//SPDIF_DDI SWITCH S1
DDI_SDATA
pin 22 istype 'com';
//EXTERNAL DATA INPUT DDI
RESET
Pin 23 istype 'com';
//Active hi reset output
to AD1896
RESET_LO
Pin 44 istype 'com';
//Active low reset input
MS_MODE2, MS_MODE1, MS_MODE0 pin 24,25,30 istype 'com'; //MASTER/SLAVE MODE SWITCH S4
IN_MODE2,IN_MODE1,IN_MODE0
pin 18,15,14 istype 'com'; //INPUT SERIAL MODE
SWITCH S3
"OUTPUTS =========================================================================
// TDO
pin 29 istype 'com';
//JTAG O/P
M0, M1, M2, M3
pin 8,9,10,11 istype 'com'; //SPDIF_RVR MODE SELECT
SMODE_I_0, SMODE_I_1, SMODE_I_2 pin 33,32,31 istype 'com'; //INPUT SERIAL MODE FORMAT
FOR AD1896
SDATA_I
pin 37 istype 'com';
//SERIAL DATA INPUT TO
AD1896 ASRC
//IO SIGNALS
DIR_FSYNC, DIR_SCLK
IO'S
DDI_LRCLK, DDI_SCLK
SCLK IO'S FOR HDR3
LRCLK_I, SCLK_I
AD1896 ASRC
pin 2,3;
pin 21,20;
pin 35,36;
//DIR_FYSNC AND DIR_SCLK
//EXTERNAL LRCLK AND
//LRCLK_I AND SCLK_I IO'S TO
"NODES
–20–
REV. 0