EVAL-AD1896EB Datasheet, PDF (3/28 Pages) Analog Devices – AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board

EVAL-AD1896EB
S8
JP4 CRYSTAL OSC./EXTERNAL CLK
DDI-HDR3, SPDIF-J1,
TOSLINK-U4
S6
S3 (8-POSITION SWITCH)
S5
S7
GRPDLYS 1
MCLK_I 2
MCLK_O 3
SDATA_I 4
SCLK_I 5
LRCLK_I 6
VDD_IO 7
DGND 8
BYPASS 9
SMODE_IN_0 10
SMODE_IN_1 11
SMODE_IN_2 12
RESET 13
MUTE_IN 14
AD1896
28 MMODE_2
27 MMODE_1
26 MMODE_0
25 SCLK_O
24 LRCLK_O
23 SDATA_O
22 VDD_CORE
21 DGND
20 TDM_IN
19 SMODE_OUT_0
18 SMODE_OUT_1
17 WLNGTH_OUT_0
16 WLNGTH_OUT_1
15 MUTE_OUT
S4 (8-POSITION SWITCH)
DDO-HDR5, SPDIF-J2,
TDM_OUT-HDR2
TDM IN HEADER HDR1
JP1 (4-POSITION JUMPER)
Figure 1. Key Jumpers and Switches on the Evaluation Board
Pin
1
3
5
7
2, 4, 6, 8, 10
Table I. Pinout Table for 10-Pin Header Connectors
HDR1 (TDM_IN)
5 V (O)
TDM_I (I)
SCLK_O (I/O)
LRCLK_O (I/O)
GND
HDR2 (TDM_OUT)
5 V (O)
SDATA_O (O)
SCLK_O (I/O)
LRCLK_O (I/O)
GND
HDR3 (DDI)
5 V (O)
SDATA_I (I)
LRCLK_I (I/O)
SCLK_I (I/O)
GND
HDR5 (DDO)
5 V (O)
SDATA_O (O)
SCLK_O (I/O)
LRCLK_O (I/O)
GND
DIGITAL AUDIO INPUT SIGNALS
Input serial port of the AD1896 can be driven in various ways
using this evaluation board.
1. RCA phone jack (J1) or TOSLINK (U4) optical connector
can be used to input the AES/EBU or SPDIF signal to the
SPDIF receiver CS8414 (U1). SPDIF receiver generated
SCLK_I, LRCLK_I, and SDATA_I signals drive the input
serial port of the AD1896. SPDIF input is supported only
when the AD1896 serial input port is in SLAVE mode (Switch
S4 position 3 to 7) and supports all input serial data formats
except RJ-24 bit and RJ-20 bit (Switch S3 positions 2, 3). The
SPDIF receiver limits input sample rates to 96 kHz.
2. Alternatively, an external data header (HDR3) can be used
to directly source all three signals SCLK_I, LRCLK_I, and
SDATA_I from an external source. Unlike SPDIF receiver,
input sample rate up to 192 kHz is possible (input port in
slave mode) and set by an external source. All input serial
data formats and master/slave clock modes are supported.
SCLK_I and LRCLK_I signals of the input serial port are
bidirectional signals. Logic levels on pins MMODE_ [2:0]
control the direction of these signals. When the input serial port
is in master mode, these signals are generated by the AD1896;
whereas, in the slave mode these signals are provided by an
external source. MMODE_[2:0] pins are set by the 8-position
Switch S4. Tables II and III show the master/slave clock mode
corresponding to each switch position.
Input data format, such as, I²S, LJ, or RJ is set by the logic
levels on SMODE_IN_[2:0] pins as shown in Table IV. Set the
8-position Switch S3 on the evaluation board for the proper
input data format.
Table II. Input and Output Serial Port Modes
S4 Switch Position
MMODE_[2:0]
210
Master/Slave Modes
7
000
Both Serial Ports are in Slave Mode
6
001
*Output Serial Port is Master with 768 Ï« f_{S_OUT}
5
010
*Output Serial Port is Master with 512 Ï« f_{S_OUT}
4
011
*Output Serial Port is Master with 256 Ï« f_{S_OUT}
3
100
Matched Phase Mode
2
101
*Input Serial Port is Master with 768 Ï« f_{S_IN}
1
110
*Input Serial Port is Master with 512 Ï« f_{S_IN}
0
111
*Input Serial Port is Master with 256 Ï« f_{S_IN}
*In MASTER MODE operation, maximum sample rate for Master Port is limited to 96 kHz.
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