EVAL-AD1896EB Datasheet, PDF (25/28 Pages) Analog Devices – AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board

EVAL-AD1896EB
EQUATIONS
// AD1896 ASRC Output Serial Port Interface Mode and word length Select
WDLNGTH_O_1 = WDLNGTH1;
WDLNGTH_O_0 = WDLNGTH0;
SMODE_O_1 = OPMODE1;
SMODE_O_0 = OPMODE0;
// CS8414 DIT Interface Mode Select. The chip is configured in the LJ mode when AD1896 output
format are
// set either RJ24, RJ20, RJ18 or RJ16. Also need to invert the incoming SCLK signal in the
LJ24, RJ24, RJ20,
// RJ18 and RJ16 mode to match the DIT interface requirment for DIT_SCLK.
M0 = LJ;
M1 = 0;
M2 = I2S;
// AD1852 Stereo DAC input serial Interface mode select. NOTE that the DAC requires serial
programing for
// RJ20, RJ18, RJ16 mode. Since AD1896 EVB does not allow serial programming of the AD1852
registers,
// AD1852 will be configured in RJ24 mode when AD1896 output port is configured in RJ20, RJ18
and RJ16 mode.
IDPM1 = LJ;
IDPM0 = I2S;
// AD1896, DIR, DIT, AD1852 MCLK control logic. Based on the Master/Slave operation of the
AD1896 in/out ports,
// 33.8688MHz crystal frequency will be divided by either 1, 2 or 3 and the ouput of the di-
vider is feed into the DAC and DIT.
// On-board 12.288MHz clock oscillator is enabled only when input and ouput serial ports are
configured in SLAVE mode.
OSC_EN = (BOTH_SLAVE);
SLVCLK1 = (O_MAS_768) # (BOTH_SLAVE);
SLVCLK0 = (O_MAS_512) # (BOTH_SLAVE);
DIV2_3 = (!O_MAS_512) & (O_MAS_768);
// IO control logic for bi-directional signals
DDO_SCLK.OE = (O_MAS_768 # O_MAS_512 # O_MAS_256);
DDO_LRCLK.OE = (O_MAS_768 # O_MAS_512 # O_MAS_256);
SCLK_O.OE = (BOTH_SLAVE # MATCH_PHASE # IN_MAS_768 # IN_MAS_512 # IN_MAS_256);
LRCLK_O.OE = (BOTH_SLAVE # MATCH_PHASE # IN_MAS_768 # IN_MAS_512 # IN_MAS_256);
// AD1896 ASRC Output Serial port signals
DDO_SDATA = SDATA_O;
DDO_SCLK = ISCLK;
DDO_LRCLK = ILRCLK;
SCLK_O = ISCLK;
LRCLK_O = ILRCLK;
// DAC AND DIT SIGNALS
SDATA_DAC_DIT = SDATA_O;
LRCLK_DAC
= ILRCLK;
REV. 0
–25–