A3P1000-1FGG144I Datasheet, PDF (82/206 Pages) Actel Corporation – ProASIC3 Flash Family FPGAs

ProASIC3 DC and Switching Characteristics
Output Enable Register
CLK
D_Enable
50%
1
50%
t_OESUD t_OEHD
50% 0 50%
50%
50%
t_OECKMPWH t_OECKMPWL
50%
50%
50%
Enable
Preset
Clear
EOUT
50%
t_OESUEt_OEHE
t_OEWPRE
50%
t_OERECPRE
50%
t_OEWCLR t_OERECCLR
50%
50%
t_OEPRE2Q
50% 50%
t_OECLKQ
t_OECLR2Q
50%
Figure 2-18 • Output Enable Register Timing Diagram
t_OEREMPRE
50%
t_OEREMCLR
50%
2-68
v1.3