A3P1000-1FGG144I Datasheet, PDF (37/206 Pages) Actel Corporation – ProASIC3 Flash Family FPGAs

ProASIC3 DC and Switching Characteristics
Detailed I/O DC Characteristics
Table 2-27 • Input Capacitance
Symbol
Definition
Conditions
Min. Max. Units
C_IN
C_INCLK
Input capacitance
Input capacitance on the clock pin
V_IN = 0, f = 1.0 MHz
V_IN = 0, f = 1.0 MHz
8
pF
8
pF
Table 2-28 • I/O Output Buffer Maximum Resistances¹
Applicable to Advanced I/O Banks
Standard
Drive Strength
R_PULL-DOWN
(Ω)²
R_PULL-UP
(Ω)³
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
2.5 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
12 mA
25
50
16 mA
20
40
24 mA
11
22
1.8 V LVCMOS
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
12 mA
20
22
16 mA
20
22
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
12 mA
33
37
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer
resistance values depend on V_CCI, drive strength selection, temperature, and process. For
board design considerations and detailed output buffer resistances, use the corresponding
IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.
2. R_{(PULL-DOWN-MAX)} = (V_OLspec) / I_OLspec
3. R_{(PULL-UP-MAX)} = (V_CCImax – V_OHspec) / I_OHspec
v1.3
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