A3P1000-1FGG144I Datasheet, PDF (39/206 Pages) Actel Corporation – ProASIC3 Flash Family FPGAs

ProASIC3 DC and Switching Characteristics
Table 2-30 • I/O Output Buffer Maximum Resistances¹
Applicable to Standard I/O Banks
Standard
Drive Strength
R_PULL-DOWN
(Ω)²
R_PULL-UP
(Ω)³
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
2.5 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
1.8 V LVCMOS
2 mA
200
225
4 mA
100
112
1.5 V LVCMOS
2 mA
200
224
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer
resistance values depend on V_CCI, drive strength selection, temperature, and process. For
board design considerations and detailed output buffer resistances, use the corresponding
IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.
2. R_{(PULL-DOWN-MAX)} = (V_OLspec) / I_OLspec
3. R_{(PULL-UP-MAX)} = (V_CCImax – V_OHspec) / I_OHspec
Table 2-31 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
R_(WEAK
1
PULL-UP)
(Ω)
R_(WEAK
2
PULL-DOWN)
(Ω)
V_CCI
3.3 V
Min.
10 k
Max.
45 k
Min.
10 k
Max.
45 k
2.5 V
11 k
55 k
12 k
74 k
1.8 V
18 k
70 k
17 k
110 k
1.5 V
19 k
90 k
19 k
140 k
Notes:
1. R_{(WEAK PULL-UP-MAX)} = (V_OLspec) / I_{(WEAK PULL-UP-MIN)}
2. R_{(WEAK PULL-UP-MAX)} = (V_CCImax – V_OHspec) / I_{(WEAK PULL-UP-MIN)}
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