A3P1000-1FGG144I Datasheet, PDF (72/206 Pages) Actel Corporation – ProASIC3 Flash Family FPGAs

ProASIC3 DC and Switching Characteristics
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Actel Designer software when
the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also
requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
Figure 2-11. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one
receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.
The values for the three driver resistors are different from those used in the LVPECL
implementation because the output standard specifications are different.
Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
FPGA
OUTBUF_LVDS
Bourns Part Number: CAT16-LV4F12
P
165 Ω
P
Z₀ = 50 Ω
140 Ω
100 Ω
165 Ω
N
Z₀ = 50 Ω
N
FPGA
+
–
INBUF_LVDS
Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation
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