ACE25C200G Datasheet, PDF (9/48 Pages) ACE Technology Co., LTD. – 2M BIT SPI NOR FLASH

ACE25C200G
2M BIT SPI NOR FLASH
Status Register
Status Register Table
See Table 3 and Table 4 for detail description of the Status Register bits. Status Register-2 (SR2)
and Status Register-1 (SR1) can be used to provide status on the availability of the Flash memory
array, if the device is write enabled or disabled the state of write protection, Quad SPI setting, Security
Register lock status, and Erase/Program Suspend status.
Table 3 Status Register-2 (SR2)
Default
BIT
Name
Function
Value
Description
7
SUS
Suspend
0
0 = Erase/Program not suspended
Status
1 = Erase/Program suspended
6
CMP
Complement
Protect
0
0 = Normal Protection Map
1 = Inverted Protection Map
5
LB3
Security
0
OTP Lock Bits 3:1 for Security Registers 3:1
4
LB2
Register
0
3
LB1
Lock Bits
0 = Security Register not protected
0
2
Reserved Reserved
0
0 = Quad Mode Not Enabled, the /WP pin and /HOLD
are enabled.
1
QE
Quad Enable
0
1 = Quad Mode Enabled, the IO2 and IO3 pins are
enabled, and /WP and /HOLD functions are disabled
Status
0 = SRP0 selects whether /WP input has effect on
Resister
protection of the status register
0
SRP1
Protect 1
0
1 = SRP0 selects Power Supply Lock Down or OTP
Lock Down mode
VER 1.1 9