ACE25C200G Datasheet, PDF (23/48 Pages) ACE Technology Co., LTD. – 2M BIT SPI NOR FLASH

ACE25C200G
2M BIT SPI NOR FLASH
Dual I/O Fast Read with “Continuous Read Mode”
The Fast Read Dual I/O command can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 14. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O command through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O command
(after /CS is raised and then lowered) does not require the BBH instruction code, as shown in Figure
12. This reduces the command sequence by eight clocks and allows the Read address to be
immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal
to (1,0), the next command (after /CS is raised and then lowered) requires the first byte instruction
code, thus returning to normal operation. A “Continuous Read Mode” Reset command can also be
used to reset (M7-0) before issuing normal commands (see Continuous Read Mode Reset (FFH or
FFFFH)).
Figure 12 Dual I/O Fast Read Sequence Diagram (Previous command set M5-4 =10)
Figure 12
Quad I/O Fast Read (EBH)
See Figure 13, the Quad I/O Fast Read instruction is similar to the Dual I/O Fast Read instruction
but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and
4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge
of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The
first byte addressed can be at any location. The address is automatically incremented to the next
higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register
must be set to enable for the Quad I/O Fast read instruction.
Figure 13 Quad I/O Fast Read Sequence Diagram (Initial command or previous M5-4≠10)
Figure 13
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