ACE25C200G Datasheet, PDF (4/48 Pages) ACE Technology Co., LTD. – 2M BIT SPI NOR FLASH

ACE25C200G
2M BIT SPI NOR FLASH
Chip Select (/CS)
The chip select signal indicates when a instruction for the device is in process and the other signals are
relevant for the memory device. When the /CS signal is at the logic high state, the device is not selected
and all input signals are ignored and all output signals are high impedance. Unless an internal Program,
Erase or Write Status Registers embedded operation is in progress, the device will be in the Standby
Power mode. Driving the /CS input to logic low state enables the device, placing it in the Active Power
mode. After Power Up, a falling edge on /CS is required prior to the start of any instruction.
Serial Clock (SCLK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses,
or data input are latched on the rising edge of the SCLK signal. Data output changes after the falling edge
of SCLK.
Serial Input (SI)/IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and
data to be programmed. Values are latched on the rising edge of serial SCK clock signal.
SI becomes IO0 an input and output during Dual and Quad Instructions for receiving instructions,
addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well
as shifting out data (on the falling edge of SCK).
Serial Data Output (SO)/IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling
edge of the serial SCK clock signal.
SO becomes IO1 an input and output during Dual and Quad Instructions for receiving instructions,
addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well
as shifting out data (on the falling edge of SCK).
Write Protect (/WP)/IO2
When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status
Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status
Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in
the memory area that are protected by the Block Protect, TB, SEC, and CMP bits in the status registers,
are also hardware protected against data modification while /WP remains Low. The /WP function is not
available when the Quad mode is enabled (QE) in Status Register 2 (SR2[1]=1).
The /WP function is replaced by IO2 for input and output during Quad mode for receiving addresses,
and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out
data (on the falling edge of SCK). /WP has an internal pull-up resistance; when unconnected; /WP is at
VIH and may be left unconnected in the host system if not used for Quad mode.
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