ACE25C200G Datasheet, PDF (28/48 Pages) ACE Technology Co., LTD. – 2M BIT SPI NOR FLASH

ACE25C200G
2M BIT SPI NOR FLASH
Deep Power-Down (B9H)
Although the standby current during normal operation is relatively low, standby current can be
further reduced with the Deep Power-down instruction. The lower power consumption makes the
Deep Power-down (DPD) instruction especially useful for battery powered applications (see ICC1 and
ICC2). The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as
shown in Figure 19
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep
Power down instruction will not be executed. After /CS is driven high, the power-down state will
entered within the time duration of tDP. While in the power-down state only the Release from Deep
Power-down / Device ID instruction, which restores the device to normal operation, will be recognized.
All other Instructions are ignored. This includes the Read Status Register instruction, which is always
available during normal operation. Ignoring all but one instruction also makes the Power Down state a
useful condition for securing maximum write protection. The device always powers-up in the normal
operation with the standby current of ICC1.
Figure 19 Deep Power-Down Sequence Diagram
Figure 19
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