ACE25C200G Datasheet, PDF (30/48 Pages) ACE Technology Co., LTD. – 2M BIT SPI NOR FLASH

ACE25C200G
2M BIT SPI NOR FLASH
Read Security Registers (48H)
See Figure 22, the Read Security Registers instruction is similar to Fast Read instruction. The
instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in
during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each
bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed
can be at any location. The address is automatically incremented to the next higher address after
each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte
3FFH), it will reset to 000H, the instruction is completed by driving /CS high
Table 10
Address
A23-A16
A15-A8
A7-A0
Security Registers 1
00H
01H
Byte Address
Security Registers 2
00H
02H
Byte Address
Security Registers 3
00H
03H
Byte Address
Figure 22 Read Security Registers instruction Sequence Diagram
Figure 22
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