ACE25Q400G Datasheet, PDF (7/46 Pages) ACE Technology Co., LTD. – 4M BIT SPI NOR FLASH Memory Series

ACE25Q400G
4M BIT SPI NOR FLASH Memory Series
Device Operation
Standard SPI Instructions
The ACE25Q400G features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of
SCLK.
Dual SPI Instructions
The ACE25Q400G supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual
I/O Fast Read” (3BH and BBH) instructions. These instructions allow data to be transferred to or from
the device at two times the rate of the standard SPI. When using the Dual SPI instruction the SI and
SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI Instructions
The ACE25Q400G supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O
Fast Read” (6BH, EBH) instructions. These instructions allow data to be transferred t-o or from the
device at four times the rate of the standard SPI. When using the Quad SPI instruction the SI and SO
pins become bidirectional I/O pins: IO0 and IO1, and /WP and /HOLD pins become IO2 and IO3.
Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
Operation Features
Supply Voltage
Operating Supply Voltage
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified
[VCC(min), VCC(max)] range must be applied (see operating ranges of page 39). In order to secure a stable DC
supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to
100nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission
of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
Power-up Conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (/CS)
line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the /CS line to
VCC via a suitable pull-up resistor.
In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge sensitive as well as level
sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip
Select (/CS). This ensures that Chip Select (/CS) must have been High, prior to going Low to start the first operation.
Device Reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on reset (POR)
circuit is included. At Power-up, the device does not respond to any instruction until VCC has reached the power on
reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in operating ranges of
page 39).
When VCC has passed the POR threshold, the device is reset.
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