ACE25Q400G Datasheet, PDF (31/46 Pages) ACE Technology Co., LTD. – 4M BIT SPI NOR FLASH Memory Series

ACE25Q400G
4M BIT SPI NOR FLASH Memory Series
Erase Security Registers (44H)
The ACE25Q400G provides three 256-byte Security Registers which can be erased and
programmed individually. These registers may be used by the system manufacturers to store security
and other important information separately from the main memory array.
See Figure 23, the Erase Security Registers instruction is similar to Sector/Block Erase instruction.
A Write Enable instruction must previously have been executed to set the Write Enable Latch bit.
The Erase Security Registers instruction sequence: /CS goes low sending Erase Security Registers
instruction /CS goes high. /CS must be driven high after the eighth bit of the instruction code has been
latched in otherwise the Erase Security Registers instruction is not executed. As soon as /CS is driven
high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the
Erase Security Registers cycle is in progress, the Status Register may be read to check the value of
the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase
Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch bit is reset. The Security Registers Lock Bit (LB) in the Status
Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security
Registers will be permanently locked; the Erase Security Registers instruction will be ignored.
Table 11
Address
A23-A16
A15-A8
A7-A0
Security Registers 1
00H
01H
Don’t Care
Security Registers 2
00H
02H
Don’t Care
Security Registers 3
00H
03H
Don’t Care
Figure 23, Erase Security Registers instruction Sequence Diagram
Figure 23
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