ACE25Q400G Datasheet, PDF (18/46 Pages) ACE Technology Co., LTD. – 4M BIT SPI NOR FLASH Memory Series

ACE25Q400G
4M BIT SPI NOR FLASH Memory Series
Configuration and Status Instructions
Write Enable (06H)
See Figure 2, the Write Enable instruction is for setting the Write Enable Latch bit. The Write
Enable Latch bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and
Write Status Register instruction. The Write Enable instruction sequence: /CS goes low sending the
Write Enable instruction /CS goes high.
Figure 2 Write Enable Sequence Diagram
Figure 2
Write Disable (04H)
See Figure 3, the Write Disable instruction is for resetting the Write Enable Latch bit. The Write
Disable instruction sequence: /CS goes low sending the Write Disable instruction /CS goes high. The
WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register,
Page Program, Sector Erase, Block Erase and Chip Erase instructions.
Figure 3, Write Disable Sequence Diagram
Figure 3
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