ACE25Q400G Datasheet, PDF (12/46 Pages) ACE Technology Co., LTD. – 4M BIT SPI NOR FLASH Memory Series

ACE25Q400G
4M BIT SPI NOR FLASH Memory Series
Write Protect Features
1. Software Protection: The Block Protect (SEC, TB, BP2, BP1, BP0) bits define the section of the
memory array that can be read but not change.
2.Hardware Protection: /WP going low to protected the BP0~SEC bits and SRP0~1 bits.
3.Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the
Release from deep Power-Down Mode instruction.
4.Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program, Sector
Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers
instruction.
Status Register Memory Protection
Protect Table
Table 6 ACE25Q400G Status Register Memory Protection(CMP=0)
Status Register Content
Memory Content
SEC TB BP2 BP1 BP0 Blocks
Addresses
Density
Portion
X
X
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
7
070000H-07FFFFH
64KB
Upper 1/8
0
0
0
1
0
6 and 7 060000H-07FFFFH
128KB
Upper 1/4
0
0
0
1
1
4 to 7
040000H-07FFFFH
256KB
Upper 1/2
0
1
0
0
1
0
000000H-00FFFFH
64KB
Lower 1/8
0
1
0
1
0
0 and 1 000000H-01FFFFH
128KB
Lower 1/4
0
1
0
1
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/2
0
X
1
X
X
0 to 7
000000H-07FFFFH
512KB
ALL
1
0
0
0
1
7
07F000H-07FFFFH
4KB
Upper 1/128
1
0
0
1
0
7
07E000H-07FFFFH
8KB
Upper 1/64
1
0
0
1
1
7
07C000H-07FFFFH
16KB
Upper 1/32
1
0
1
0
X
7
078000H-07FFFFH
32KB
Upper 1/16
1
0
1
1
0
7
078000H-07FFFFH
32KB
Upper 1/16
1
1
0
0
1
0
000000H-00FFFFH
4KB
Lower 1/128
1
1
0
1
0
0
000000H-001FFFH
8KB
Lower 1/64
1
1
0
1
1
0
000000H-03FFFFH
16KB
Lower 1/32
1
1
1
0
X
0
000000H-007FFFH
32KB
Lower 1/16
1
1
1
1
0
0
000000H-007FFFH
32KB
Lower 1/16
1
X
1
1
1
0 to 7
000000H-07FFFFH
512KB
ALL
VER 1.2 12