ACE25C160G Datasheet, PDF (6/36 Pages) ACE Technology Co., LTD. – Uniform SECTOR Dual and Quad Serial Flash

ACE25C160G
Uniform SECTOR Dual and Quad Serial Flash
Data Protection
The ACE25C160G provide the following data protection methods:
 Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL).
The WEL bit will return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register(WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
 Software Protection Mode: The Block Protect (SEC, TB, BP2, BP1, BP0) bits define the section
of the memory array that can be read but not change.
 Hardware Protection Mode: WP# going low to protected the BP0~SEC bits and SRP0~1 bits.
 Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the
Release from deep Power-Down Mode command.
Table1.0 ACE25C160G Protected area size (CMP=0)
Status Register Content
Memory Content
SEC TB BP2 BP1 BP0 Blocks
Addresses
Density
Portion
XX0
0
0 NONE
NONE
NONE
NONE
000
0
1
31
1F0000H-1FFFFFH 64KB
Upper 1/32
000
1
0 30 to 35 1E0000H-1FFFFFH 128KB Upper 1/16
000
1
1 28 to 31 1C0000H-1FFFFFH 256KB
Upper 1/8
001
0
0 24 to 31 180000H-1FFFFFH 512KB
Upper 1/4
001
0
1 16 to 31 100000H-1FFFFFH
1M
Upper 1/2
010
0
1
0 to 1
000000H-00FFFFH
64KB
Lower 1/32
010
1
0
0 to 1
000000H-01FFFFH 128KB Lower 1/16
010
1
1
0 to 3
000000H-03FFFFH 256KB
Lower 1/8
011
0
0
0 to 7
000000H-07FFFFH 512KM
Lower 1/4
011
0
1 0 to 15 000000H-0FFFFFH
1M
Lower 1/2
XX1
1
X 0 to 31 000000H-1FFFFFH
2M
ALL
100
0
1
31
1FF000H-1FFFFFH
4KB
Top Block
100
1
0
31
1FE000H-1FFFFFH
8KB
Top Block
100
1
1
31
1FC000H-1FFFFFH 16KB
Top Block
101
0
X
31
1F8000H-1FFFFFH 32KB
Top Block
110
0
1
0
000000H-000FFFH
4KB Bottom Block
110
1
0
0
000000H-001FFFH
8KB Bottom Block
110
1
1
0
000000H-003FFFH
16KB ^{Bottom Block}
111
0
X
0
000000H-007FFFH
32KB ^{Bottom Block}
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