ACE25C160G Datasheet, PDF (17/36 Pages) ACE Technology Co., LTD. – Uniform SECTOR Dual and Quad Serial Flash

ACE25C160G
Uniform SECTOR Dual and Quad Serial Flash
Figure11. Dual I/O Fast Read Sequence Diagram (M7-0= AXH)
Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the
capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy
clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK,
then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command
sequence is shown in followed Figure12. The first byte addressed can be at any location. The address
is automatically incremented to the next higher address after each byte of data is shifted out. The
Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read
command.
Quad I/O Fast Read With “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M7-0) =AXH, then the next Quad I/O Fast Read command (after CS# is raised and then
lowered) does not require the EBH command code. The command sequence is shown in followed
Figure13. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next
command requires the first EBH command code, thus returning to normal operation. A “Continuous
Read Mode” Reset command can be used to reset (M7-0) before issuing normal command.
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