ACE25C160G Datasheet, PDF (26/36 Pages) ACE Technology Co., LTD. – Uniform SECTOR Dual and Quad Serial Flash

ACE25C160G
Uniform SECTOR Dual and Quad Serial Flash
Continuous Read Mode Reset (CRMR) (FFH)
The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to
further reduce command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read
operations do not require the BBH/EBH/E7H command code.
Because the ACE25C160G has no hardware reset pin, so if Continuous Read Mode bits are set to
“AXH”, the ACE25C160G will not recognize any standard SPI commands. So Continuous Read Mode
Reset command will release the Continuous Read Mode from the “AXH” state and allow standard SPI
command to be recognized. The command sequence is show in Figure24.
Figure24. Continuous Read Mode Reset Sequence Diagram
Erase Security Registers (44H)
The ACE25C160G provides four 256-byte Security Registers which can be erased and
programmed individually. These registers may be used by the system manufacturers to store
security and other important information separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable
(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low sending Erase Security
Registers command CS# goes high. The command sequence is shown in Figure33. CS# must be
driven high after the eighth bit of the command code has been latched in otherwise the Erase
Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase
Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers
cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB) in the Status Register can be
used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be
permanently locked; the Erase Security Registers command will be ignored.
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