Z86E61 Datasheet, PDF (7/44 Pages) Zilog, Inc. – CMOS Z8 16K/32K EPROM MICROCONTROLLER

PIN FUNCTIONS
PRELIMINARY
Z86E61/E63 Z8^® MCU
WITH 16K/32K EPROM
ROMless (input, active Low). Connecting this pin to GND
disables the internal ROM and forces the device to func-
tion as a Z86C91 ROMless Z8 (see the Z86C91 product
specification for more information). When left unconnected
or pulled High to V , the device functions as a normal
CC
Z86E61/E63 EPROM version. Note: This pin is only avail-
able on the 44-pin versions of the Z86E61/E63.
/DS (output, active Low). Data Strobe is activated once for
each external memory transfer. For a READ operation,
data must be available prior to the trailing edge of /DS. For
WRITE operations, the falling edge of /DS indicates that
output data is valid.
/AS (output, active Low). Address Strobe is pulsed once at
the beginning of each machine cycle. Address output is
through Port 1 for all external programs. Memory address
transfers are valid at the trailing edge of /AS. Under
program control, /AS can be placed in the high-
impedance state along with Ports 0 and 1, Data Strobe,
and Read/Write.
XTAL2, XTAL1 Crystal 2, Crystal 1 (time-based input and
output, respectively). These pins connect a parallel-
resonant crystal, ceramic resonator, LC, or any external
single-phase clock to the on-chip oscillator and buffer.
R//W (output, write Low). The Read/Write signal is Low
when the MCU is writing to the external program or data
memory.
/RESET (input, active Low). To avoid asynchronous and
noisy reset problems, the Z86E61/E63 is equipped with a
reset filter of four external clocks (4TpC). If the external
/RESET signal is less than 4TpC in duration, no reset
occurs.
On the fifth clock after the /RESET is detected, an internal
RST signal is latched and held for an internal register count
of 18 external clocks, or for the duration of the external
/RESET, whichever is longer. During the reset cycle, /DS is
held active Low while /AS cycles at a rate of TpC/2. When
/RESET is deactivated, program execution begins at loca-
tion 000C (HEX). Power-up reset time must be held low for
50 ms, or until V is stable, whichever is longer.
CC
Port 0 (P07-P00). Port 0 is an 8-bit, nibble programmable,
bidirectional, TTL compatible port. These eight I/O lines
can be configured under software control as a nibble I/O
port, or as an address port for interfacing external memory.
When used as an I/O port, Port 0 may be placed under
handshake control. In this configuration, Port 3, lines P32
and P35 are used as the handshake control /DAV0 and
RDY0 (Data Available and Ready). Handshake signal
assignment is dictated by the I/O direction of the upper
nibble P07-P04. The lower nibble must have the same
direction as the upper nibble to be under handshake
control.
For external memory references, Port 0 can provide ad-
dress bits A11-A8 (lower nibble) or A15-A8 (lower and
upper nibbles) depending on the required address space.
If the address range requires 12 bits or less, the upper
nibble of Port 0 can be programmed independently as I/O
while the lower nibble is used for addressing. If one or both
nibbles are needed for I/O operation, they must be config-
ured by writing to the Port 0 Mode register.
In ROMless mode, after a hardware reset, Port 0 lines are
defined as address lines A15-A8, and extended timing is
set to accommodate slow memory access. The initializa-
tion routine can include reconfiguration to eliminate this
extended timing mode (Figure 8).
Port 1 (P17-P10). Port 1 is an 8-bit, byte programmable,
bidirectional, TTL compatible port. It has multiplexed Ad-
dress (A7-A0) and Data (D7-D0) ports. For Z86E61/E63,
these eight I/O lines can be programmed as input or output
lines or are configured under software control as an
address/data port for interfacing external memory. When
used as an I/O port, Port 1 can be placed under handshake
control. In this configuration, Port 3 lines, P33 and P34, are
used as the handshake controls RDY1 and /DAV1.
Memory locations greater than 16384 (E61) or 32768 (E63)
are referenced through Port 1. To interface external memory,
Port 1 must be programmed for the multiplexed Address/
Data mode. If more than 256 external locations are re-
quired, Port 0 must output the additional lines.
Port 1 can be placed in high-impedance state along with
Port 0, /AS, /DS, and R//W, allowing the MCU to share
common resources in multiprocessor and DMA applica-
tions. Data transfers are controlled by assigning P33 as a
Bus Acknowledge input, and P34 as a Bus Request output
(Figure 9).
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