Z86E61 Datasheet, PDF (41/44 Pages) Zilog, Inc. – CMOS Z8 16K/32K EPROM MICROCONTROLLER

PRELIMINARY
Z86E61/E63 Z8^® MCU
WITH 16K/32K EPROM
OPCODE MAP
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
6.5
6.5
6.5
6.5 10.5 10.5 10.5 10.5 6.5
0 DEC DEC ADD ADD ADD ADD ADD ADD LD
6.5 12/10.5 12/10.0 6.5 12.10.0 6.5
LD DJNZ JR LD
JP INC
R1
IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM r1, R2 r2, R1 r1, RA cc, RA r1, IM cc, DA r1
6.5
6.5
6.5
6.5 10.5 10.5 10.5 10.5
1 RLC RLC ADC ADC ADC ADC ADC ADC
R1
IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
6.5
6.5
6.5
6.5 10.5 10.5 10.5 10.5
2
INC INC SUB SUB SUB SUB SUB SUB
R1
IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
8.0 6.1
6.5
6.5 10.5 10.5 10.5 10.5
3
JP SRP SBC SBC SBC SBC SBC SBC
IRR1 IM r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
8.5
8.5
6.5
6.5 10.5 10.5 10.5 10.5
4
DA
DA OR OR OR OR OR OR
R1
IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
10.5 10.5 6.5
6.5 10.5 10.5 10.5 10.5
5
POP POP AND AND AND AND AND AND
R1
IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
6.5
6.5
6.5
6.5 10.5 10.5 10.5 10.5
6 COM COM TCM TCM TCM TCM TCM TCM
6.0
STOP
R1
IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
10/12.1 12/14.1 6.5
7 PUSH PUSH TM
6.5 10.5 10.5 10.5 10.5
TM
TM
TM
TM
TM
7.0
HALT
R2 IR2 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
10.5 10.5 12.0 18.0
6.1
8 DECW DECW _{LDE LDEI}
DI
RR1 IR1 r1, Irr2 Ir1, Irr2
6.5
6.5 12.0 18.0
6.1
9
RL
RL LDE LDEI
EI
R1
IR1 r2, Irr1 Ir2, Irr1
10.5 10.5 6.5
6.5 10.5 10.5 10.5 10.5
A INCW INCW CP
CP
CP
CP
CP CP
14.0
RET
RR1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
6.5
6.5
6.5
6.5 10.5 10.5 10.5 10.5
B CLR CLR XOR XOR XOR XOR XOR XOR
16.0
IRET
R1
IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
6.5
6.5 12.0 18.0
10.5
C
RRC RRC LDC LDCI
LD
6.5
RCF
R1
IR1 r1, Irr2 Ir1, Irr2
r1,x,R2
6.5
6.5
12.0 18.0 20.0
D SRA SRA LDC LDCI CALL*
20.0 10.5
CALL LD
6.5
SCF
R1
IR1 r1, Irr2 Ir1, Irr2 IRR1
DA r2,x,R1
6.5
6.5
E
RR
RR
6.5 10.5 10.5 10.5 10.5
LD
LD
LD
LD
LD
6.5
CCF
R1
IR1
r1, IR2 R2, R1 IR2, R1 R1, IM IR1, IM
8.5
8.5
6.5
10.5
F SWAP SWAP
LD
LD
6.0
NOP
R1
IR1
Ir1, r2
R2, IR1
2
3
2
3
1
Bytes per Instruction
Execution
Cycles
Lower
Opcode
Nibble
4
Upper
Opcode
Nibble
10.5
A CP
R1, R2
Pipeline
Cycles
Mnemonic
Legend:
R = 8-bit Address
r = 4-bit Address
R1 or r1 = Dst Address
R2 or r2 = Src Address
Sequence:
Opcode, First Operand,
Second Operand
First
Operand
Second
Operand
Note: Blank areas not defined.
*2-byte instruction appears as
a 3-byte instruction
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