Z86E61 Datasheet, PDF (17/44 Pages) Zilog, Inc. – CMOS Z8 16K/32K EPROM MICROCONTROLLER

PRELIMINARY
Z86E61/E63 Z8^® MCU
WITH 16K/32K EPROM
Clock. The Z86E61/E63 on-chip oscillator has a high
gain, parallel resonant amplifier for connection to a crystal,
LC, ceramic resonator, or any suitable external clock
source (XTAL1 = Input, XTAL2 = Output). The crystal
should be AT cut, 1 MHz to 16 MHz max; series resistance
(RS) is less than or equal to 100 Ohms. The crystal should
be connected across XTAL1 and XTAL2 using the recom-
mended capacitors (10 pF < CL < 100 pF) from each pin
to ground (Figure 17). Note: Actual capacitor value speci-
fied by crystal manufacturer.
C1
Pin 11
C2
XTAL1
C1
Pin 11
XTAL2
C2
Pin 11
XTAL1
L
XTAL2
Pin 11
Ceramic Resonator
or Crystal
LC Clock
XTAL1
XTAL2
External Clock
Figure 17. Oscillator Configuration
HALT. Turns off the internal CPU clock but not the XTAL
oscillation. The counter/timers and external interrupts IRQ0,
IRQ1, IRQ2, and IRQ3 remain active. The devices are
recovered by interrupts, either externally or internally gen-
erated. An interrupt request must be executed (enabled)
to exit HALT mode. After the interrupt service routine, the
program continues from the instruction after the HALT.
STOP. This instruction turns off the internal clock and
external crystal oscillation, and reduces the standby cur-
rent to 5 µA (typical) or less. The STOP mode is terminated
by a reset, which causes the processor to restart the
application program at address 000C (HEX).
In order to enter STOP (or HALT) mode, it is necessary to
first flush the instruction pipeline to avoid suspending
execution in mid-instruction. To do this, the user must
execute a NOP (opcode = OFFH) immediately before the
appropriate SLEEP instruction. i.e.,
FF NOP
6F STOP
or
FF NOP
7F HALT
; clear the pipeline
; enter STOP mode
; clear the pipeline
; enter HALT mode
PROGRAMMING
Z86E61/E63 User Modes
The Z86E61/E63 uses separate AC timing cycles for the
different User Modes available. Table 6 shows the Z86E61/
E63 User Modes. Table 7 shows the timing of the program-
ming waveforms.
User MODE 1 EPROM Read
The Z86E61/E63 EPROM read cycle is provided so that the
user may read the Z86E61/E63 as a standard 27128 (E61)
or 27256 (E63) EPROM. This is accomplished by driving
the /EPM pin (P32) to V_H and activating /CE and /OE. /PGM
remains inactive. This mode is not valid after execution of
an EPROM protect cycle. Timing for the EPROM read cycle
is shown in Figure 18.
User MODE 2 EPROM Program
The Z86E61/E63 Program function conforms to the Intelli-
gent programming algorithm. The device is programmed
with V_CC at 6.0V and V_PP = 12.5V. Programming pulses are
applied in 1 ms increments to a maximum of 25 pulses
before proper verification. After verification, a program-
ming pulse of three times the duration of the cycles
necessary to program the device is issued to ensure
proper programming. After all addresses are programmed,
a final data comparison is executed and the programming
cycle is complete. Timing for the Z86E61/E63 program-
ming cycle is shown in Figure 18.
17