Z86E61 Datasheet, PDF (18/44 Pages) Zilog, Inc. – CMOS Z8 16K/32K EPROM MICROCONTROLLER

PRELIMINARY
Z86E61/E63 Z8^® MCU
WITH 16K/32K EPROM
PROGRAMMING (Continued)
User Mode 3: PROM Verify
The Program Verify cycle is used as part of the intelligent
programming algorithm to insure data integrity under
worst-case conditions. It differs from the EPROM Read
cycle in that V is active and V must be driven to 6.0V.
PP
CC
Timing is shown in Figure 18.
User Modes 4 and 5: EPROM and RAM Protect
To extend program security, EPROM and RAM protect
cycles are provided for the Z86E61/E63. Execution of the
EPROM protect cycle prohibits proper execution of the
EPROM Read, EPROM Verify, and EPROM programming
cycles. Execution of the RAM protect cycle disables ac-
cesses to the upper 128 bytes of register memory (exclud-
ing mode and configuration registers), but first the user’s
program must set bit 6 of the IMR (R251). Timing is shown
in Figures 20 and 21.
User Modes. Table 6 shows the programming voltage of
each mode of the Z86E61/E63.
Table 6. OTP Programming Table
User/Test Mode
Device Pin No.
User Modes
Device Pins
P33
P32
P30
P31
V_PP
EPM
/CE
/OE
EPROM Read
Program
Program Verify
EPROM Protect
RAM Protect
V_IH
V_H
V_PP
X
V_PP
X
V_PP
V_H
V_PP
X
V_IL
V_IL
V_IL
V_IH
V_IL
V_IL
V_H
V_IH
V_H
V_IH
Notes:
V_PP = 12.0V ± 0.5V
V_H = 12.0V ± 0.5V
V_IH = 5V
V_IL = 0V
XX = Irrelevant
I_PP during programming = 40 mA maximum.
I_CC during programming, verify, or read = 40 mA maximum.
P20
/PGM
V_IH
V_IL
V_IH
V_IL
V_IL
ADDR
Addr
Addr
Addr
XX
XX
V_CC
5.0V
6.0V
6.0V
6.0V
6.0V
Port 1
CNFG
Data
Out
In
Out
XX
XX
Z86E63 Signal Description for EPROM
Program/Read
The following signals are required to correctly program or
read the Z86E63 device.
ADDR. The address must remain stable throughout the
program read cycle.
DATA. The I/O data bus must be stable during program-
ming (/OE High, /PGM Low, V High). During read the data
PP
bus outputs data.
XCLK. A clock is required to clock the /RESET signal into
the registers before programming.
A constant clock can be applied, or the XCLK input can be
toggled a minimum of 12 cycles before any programming
or verify function begins. The maximum clock frequency to
be applied when in the EPROM mode is 12 MHz.
/RESET. The reset input can be held to a constant Low or
High value throughout normal programming. It must be
held High to program the EPROM protect option bit. Also,
any time the /RESET input changes state the XCLK must be
clocked a minimum of 12 times to clock the /RESET
through the reset filter.
/OE. When the device is placed in EPROM mode, the /OE
input also serves as the precharge for the sense amp. The
precharge signal should be Low for the first half of the
stable address and High for the second half. The PRECHG
signal is inverted from the /OE signal so the /OE should be
High on the first half and Low on the second half, or stable
address. The EPROM output data should be sampled
during the second half of stable address.
The access time of the EPROM is defined in later sections.
This two part calculation of access time is required be-
cause this is a precharged sense amp with a precharge
clock.
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