Z86L70 Datasheet, PDF (47/61 Pages) Zilog, Inc. – IR/Low-Voltage Microcontroller

Zilog
Z86L70/71/75/C71
IR/Low-Voltage Microcontroller
Watch-Dog Timer Mode Register (WDTMR). The WDT time-out period. Bit 2 determines whether the WDT is ac-
is a retriggerable one-shot timer that resets the Z8 if it tive during HALT and Bit 3 determines WDT activity during
1 ^{reaches its terminal count. The WDT must initially be en- STOP. Bits 5 through 7 are reserved (Figure 37). This reg-}
abled by executing the WDT instruction and refreshed on ister is accessible only during the first 64 processor cycles
subsequent executions of the WDT instruction. The WDT (128 XTAL clocks) from the execution of the first instruc-
circuit is driven by an on-board RC oscillator or external tion after Power-On-Reset, Watch-Dog Reset, or a Stop-
oscillator from the XTAL1 pin. The WDT instruction affects Mode Recovery (Figure 40). After this point, the register
the Zero (Z), Sign (S), and Overflow (V) flags.
cannot be modified by any means, intentional or other-
wise. The WDTMR cannot be read and is located in Bank
The POR clock source is selected with bit 4 of the WDT _{F of the Expanded Register Group at address location}
register. Bit 0 and 1 control a tap circuit that determines the _{0FH. It is organized as follows:}
WDTMR (0F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
WDT TAP
00
01 *
10
11
INT RC OSC
5 ms
10 ms
20 ms
80 ms
External Clock
256 TpC
512 TpC
1024 TpC
4096 TpC
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Chip RC *
1 XTAL
Reserved (Must be 0)
Figure 37. Watch-Dog Timer Mode Register
(Write Only)
DS97LVO0500
PRELIMINARY
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