Z86L70 Datasheet, PDF (40/61 Pages) Zilog, Inc. – IR/Low-Voltage Microcontroller

Z86L70/71/75/C71
IR/Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Table 3. Interrupt Types, Sources, and Vectors
Name
IRQ0
IRQ1,
IRQ2
IRQ3
IRQ4
Source
/DAV0, IRQ0
IRQ1
/DAV2, IRQ2,
T_IN
T16
T8
Vector
Location
Comments
0, 1 External (P32),
Rising Falling Edge
Triggered
2, 3 External (P33),
Falling Edge
Triggered
4, 5 External (P31),
Rising Falling Edge
Triggered
6, 7 Internal
8, 9 Internal
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder controlled by
the Interrupt Priority register. An interrupt machine cycle is
activated when an interrupt request is granted. This dis-
ables all subsequent interrupts, saves the Program
Counter and Status Flags, and then branches to the pro-
gram memory vector location reserved for that interrupt.
All Z86L7X interrupts are vectored through locations in the
program memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request register is polled to determine which
of the interrupt requests need service.
An interrupt resulting from AN1 (P31) is mapped into IRQ2,
and an interrupt from AN2 (P32) is mapped into IRQ0. In-
terrupts IRQ2 and IRQ0 may be rising, falling, or both edge
triggered, and are programmable by the user. The soft-
ware can poll to identify the state of the pin.
Programming bits for the Interrupt Edge Select are located
in the IRQ Register (R250), bits D7 and D6 . The configu-
ration is shown in Table 4.
Table 4. IRQ Register
IRQ
Interrupt Edge
D7
D6
IRQ2 (P31) IRQ0 (P32)
0
0
F
F
0
1
F
R
1
0
R
F
1
1
R/F
R/F
Notes:
F = Falling Edge
R = Rising Edge
In analog mode, the Stop-Mode Recovery sources selected by
the SMR register are connected to the IRQ1 input. Any of the
Stop-Mode Recovery sources for SMR (except P31, P32, and
P33) can be used to generate IRQ1 (falling edge triggered)
Clock. The Z86L7X on-chip oscillator has a high-gain, par-
allel-resonant amplifier for connection to a crystal, LC, ce-
ramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 1 MHz to 8 MHz maximum, with a series resistance
(RS) less than or equal to 100 Ohms. The Z86L7X on-chip
oscillator may be driven with a cost-effective RC network
or other suitable external clock source.
The crystal should be connected across XTAL1 and
XTAL2 using the recommended capacitors (capacitance
greater than or equal to 22 pF) from each pin to ground.
The RC oscillator configuration is an external resistor con-
nected from XTAL1 to XTAL2, with a frequency-setting ca-
pacitor from XTAL1 to ground (Figure 8).
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PRELIMINARY
DS97LVO0500