Z86L70 Datasheet, PDF (43/61 Pages) Zilog, Inc. – IR/Low-Voltage Microcontroller

Zilog
Z86L70/71/75/C71
IR/Low-Voltage Microcontroller
Comparator Output Port 3 (D0). Bit 0 controls the com- cept bit 7, which is read only. Bit 7 is a flag bit that is hard-
parator used in Port 3. A 1 in this location brings the com- ware set on the condition of STOP recovery and reset by
parator outputs to P34 and P37, and a 0 releases the Port
to its standard I/O configuration.
a power-on cycle. Bits D2, D3, and D4, of the SMR regis-
ter, specify the source of the Stop-Mode Recovery signal.
1
Bit D0 determines if SCLK/TCLK are divided by 16 or not.
Stop-Mode Recovery Register (SMR). This register se- _{The SMR is located in Bank F of the Expanded Register}
lects the clock divide value and determines the mode of _{Group at address 0BH.}
Stop-Mode Recovery (Figure 33). All bits are write only ex-
SMR (0F) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF **
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
0 11 P32
100 P33
101 P27
11 0 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON *
Reserved
0 Low *
Reserved Must be 0
Stop Flag
0 POR *
1 Stop Recovery * *
* Default Setting After Reset
** Default Setting After Reset and Stop-Mode Recovery
Figure 33. Stop-Mode Recovery Register
DS97LVO0500
PRELIMINARY
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