Z86L70 Datasheet, PDF (11/61 Pages) Zilog, Inc. – IR/Low-Voltage Microcontroller

Zilog
Z86L70/71/75/C71
IR/Low-Voltage Microcontroller
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table
T_A = 0°C to +70°C
1
8.0 MHz
No
Symbol
Parameter
V_CC
Min
Max
Units Notes
1 TdA(AS)
Address Valid to /AS
2.0V
55
Rising Delay
3.9V
55
2 TdAS(A)
/AS Rising to Address 2.0V
70
Float Delay
3.9V
70
3 TdAS(DR)
/AS Rising to Read
Data Required Valid
2.0V
3.9V
4 TwAS
/AS Low Width
2.0V
80
3.9V
80
ns
2
ns
ns
2
ns
400
ns
1,2
400
ns
ns
2
ns
5 Td
Address Float to /DS
2.0V
0
Falling
3.9V
0
6 TwDSR
/DS (Read) Low Width 2.0V
300
3.9V
300
7 TwDSW
/DS (Write) Low Width 2.0V
165
3.9V
165
8 TdDSR(DR) /DS Falling to Read
Data Required Valid
2.0V
3.9V
9 ThDR(DS) Read Data to
2.0V
0
/DS Rising Hold Time
3.9V
0
ns
ns
ns
1,2
ns
ns
1,2
ns
260
ns
1,2
260
ns
ns
2
ns
10 TdDS(A)
/DS Rising to Address 2.0V
85
Active Delay
3.9V
85
11 TdDS(AS) /DS Rising to /AS
2.0V
60
3.9V
70
12 TdR/W(AS) R//W Valid to /AS
2.0V
70
Rising Delay
3.9V
70
13 TdDS(R/W) /DS Rising to
R//W Not Valid
2.0V
70
3.9V
70
14 TdDW(DSW) Write Data Valid to
2.0V
80
/DS Falling (Write)
3.9V
80
Delay
15 TdDS(DW) /DS Rising to Write
2.0V
70
Data Not Valid Delay
3.9V
80
16 TdA(DR)
Address Valid to Read
Data Required Valid
2.0V
3.9V
17 TdAS(DS) /AS Rising to /DS
2.0V
100
Falling Delay
3.9V
100
18 TdM(AS)
/DM Valid to /AS
2.0V
55
Falling Delay
3.9V
55
ns
2
ns
ns
2
ns
ns
2
ns
ns
2
ns
ns
2
ns
ns
2
ns
475
ns
1,2
475
ns
ns
2
ns
ns
2
ns
19 TdDS(DM) /DS Rise to /DM Valid
2.0V
70
ns
Delay
3.9V
70
ns
20 ThDS(A)
/DS Rise to Address
2.0V
70
ns
Valid Hold Time
3.9V
70
ns
Notes:
1. When using extended memory timing add 2 TpC.
2. Timing numbers given are for minimum TpC.
Standard Test Load
All timing references use 0.9 V_CC for a logic 1 and 0.1 V_CC for a logic 0.
DS97LVO0500
PRELIMINARY
1-11